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50RXCPPIInterruptConditionStatusandClearRegisters.............................................................89
51TXCPPIInterruptConditionStatusandClearRegisters.............................................................89
52LSUInterruptConditionStatusandClearRegisters..................................................................90
53Error,Reset,andSpecialEventInterruptConditionStatusandClearRegisters.................................91
54Doorbell0InterruptConditionRoutingRegisters......................................................................94
55RXCPPIInterruptConditionRoutingRegisters........................................................................94
56TXCPPIInterruptConditionRoutingRegisters........................................................................95
57LSUInterruptConditionRoutingRegisters.............................................................................96
58Error,Reset,andSpecialEventInterruptConditionRoutingRegisters............................................97
59InterruptStatusDecodeRegister(INTDSTn_DECODE).............................................................98
60InterruptSourcesAssignedtoISDRBits...............................................................................98
61ExampleDiagramofInterruptStatusDecodeRegisterMapping....................................................99
62INTDSTn_RATE_CNTLInterruptRateControlRegister............................................................100
63PeripheralIDRegister(PID)-AddressOffset0000h................................................................111
64PeripheralControlRegister(PCR)-AddressOffset0004h.........................................................112
65PeripheralSettingsControlRegister(PER_SET_CNTL)(AddressOffset0020h)...............................113
66PeripheralGlobalEnableRegister(GBL_EN)(AddressOffset0030h)...........................................116
67PeripheralGlobalEnableStatusRegister(GBL_EN_STAT)-Address0034h..................................117
68BlocknEnableRegister(BLKn_EN)...................................................................................119
69BlocknEnableStatusRegister(BLKn_EN)..........................................................................120
70RapidIODEVICEID1Register(DEVICEID_REG1)(Offset0080h)................................................121
71RapidIODEVICEID2Register(DEVICEID_REG2)(Offset0x0084)...............................................122
72PacketForwardingRegisternfor16-BitDeviceIDs(PF_16B_CNTLn)..........................................123
73PacketForwardingRegisternfor8-BitDeviceIDs(PF_8B_CNTLn).............................................124
74SERDESReceiveChannelConfigurationRegistern(SERDES_CFGRXn_CNTL).............................125
75SERDESTransmitChannelConfigurationRegistern(SERDES_CFGTXn_CNTL).............................128
76SERDESMacroConfigurationRegistern(SERDES_CFGn_CNTL)..............................................130
77DoorbellnInterruptConditionStatusRegister(DOORBELLn_ICSR).............................................132
78DoorbellnInterruptConditionClearRegister(DOORBELLn_ICCR)..............................................133
79RXCPPIInterruptConditionStatusRegister(RX_CPPI_ICSR)-AddressOffset0240h......................134
80RXCPPIInterruptConditionClearRegister(RX_CPPI_ICCR)-AddressOffset0248h.......................135
81TXCPPIInterruptConditionStatusRegister(TX_CPPI_ICSR)-AddressOffset0250h.......................136
82TXCPPIInterruptConditionClearRegister(TX_CPPI_ICCR)-AddressOffset0258h........................137
83LSUInterruptConditionStatusRegister(LSU_ICSR)-AddressOffset0260h..................................138
84LSUInterruptConditionClearRegister(LSU_ICCR)-AddressOffset0268h...................................141
85Error,Reset,andSpecialEventInterruptConditionStatusRegister(ERR_RST_EVNT_ICSR)-Address
Offset0270h...............................................................................................................142
86Error,Reset,andSpecialEventInterruptConditionClearRegister(ERR_RST_EVNT_ICCR)-Address
Offset0278h...............................................................................................................143
87DoorbellnInterruptConditionRoutingRegisters.....................................................................144
88RXCPPIInterruptConditionRoutingRegisters......................................................................145
89TXCPPIInterruptConditionRoutingRegisters......................................................................146
90LSUInterruptConditionRoutingRegisters............................................................................147
91Error,Reset,andSpecialEventInterruptConditionRoutingRegisters...........................................149
92InterruptStatusDecodeRegister(INTDSTn_DECODE)............................................................150
93INTDSTnInterruptRateControlRegister(INTDSTn_RATE_CNTL)..............................................154
94LSUnControlRegister0(LSUn_REG0)...............................................................................155
95LSUnControlRegister1(LSUn_REG1)...............................................................................156
96LSUnControlRegister2(LSUn_REG2)...............................................................................157
97LSUnControlRegister3(LSUn_REG3)...............................................................................158
98LSUnControlRegister4(LSUn_REG4)...............................................................................159
99LSUnControlRegister5(LSUn_REG5)...............................................................................160
100LSUnControlRegister6(LSUn_REG6)...............................................................................161
101LSUnCongestionControlFlowMaskRegister(LSUn_FLOW_MASKS).........................................162
SPRUE13A–September2006ListofFigures7
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