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CPPIblock
CPU
DMA
Configbusaccess
L2memory
Buffer
descriptor
dual-port
SRAM
(Nx20B)
Data buffer
Peripheralboundary
32
32
32
128
CPPI control
registers
2.3.4.2TXOperation
SRIOFunctionalDescription
Figure21.CPPIBoundaryDiagram
Outgoingmessagesarehandledsimilarly,withbufferdescriptorqueuesthatareassignedbytheCPUs.
Thequeuesareconfiguredandinitializeduponreset.WhenaCPUwantstosendamessagetoan
externalRapidIOdevice,itwritesthebufferdescriptorinformationviatheconfigurationbusintothe
SRAM.Again,thereisasinglebufferdescriptorperRapidIOmessage.Uponcompletionofwritingthe
bufferdescriptor,theOWNERSHIPbitissettogivecontroltotheperipheral.TheCPUthenwritestheTX
DMAStateHDPregistertoinitiatethequeuetransmit.ForTXoperation,PortIDisspecifiedtodirectthe
outgoingpackettotheappropriateport.Table19andTable20describetheTXDMAstateregisters.
Figure22showstheTXbufferdescriptorfieldsandTable21describesthem.ATXbufferdescriptorisa
contiguousblockoffour32-bitdatawordsalignedona32-bitboundary.
Table19.TXDMAStateHeadDescriptorPointer(HDP)(AddressOffset500h–53Ch)
BitNameDescription
31–0TXQueueHeadTXQueueHeadDescriptorPointer:ThisfieldistheDSPcorememoryaddressforthefirstbuffer
DescriptorPointerdescriptorinthetransmitqueue.ThisfieldiswrittenbytheDSPcoretoinitiatequeuetransmit
operationsandiszeroedbytheportwhenallpacketsinthequeuehavebeentransmitted.Anerror
conditionresultsiftheDSPcorewritesthisfieldwhenthecurrentfieldvalueisnonzero.The
addressmustbe32-bitwordaligned.
SPRUE13A–September2006SerialRapidIO(SRIO)51
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