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InterruptConditions
TheinterruptstatusbitsfoundintheERR_RST_EVNT(0x0270)canbeclearedbywritingtotheICCR
register(0x0278)inthesamemannerasotherinterrupts.However,inorderforneweventdetectionand
interruptgenerationtooccurforthesespecialinterrupts,additionalregisterbitsmustbecleared.The
followingtablenotestheadditionalinterruptsourceregisterbitsthatneedtobeclearedandthe
appropriatedsequence.TheseareallthebitsthatcancausetheERR_RST_EVNTstatusbitstobeset
Table38.InterruptClearingSequenceforSpecialEventInterrupts
InterruptFunction1
st
Step2
nd
Step3
rd
Step
MulticastEventControlSymbolWrite1toclear:Write1toclear:
receivedonanyport
Offset0x0278Offset0x12004
ERR_RST_EVNT_ICCR[0]SP_IP_MODE[4]
PortWriteInRequestreceivedWrite1toclear:Write1toclear:
onanyport
Offset0x0278Offset0x12004
ERR_RST_EVNT_ICCR[1]SP_IP_MODE[0]
Port0ErrorWrite1toclear:Write1toclearanyoftheWrite1toclear:
followingpossiblebits:
Offset0x0278Offset0x2040Offset0x14004
ERR_RST_EVNT_ICCR[8]SP0_ERR_STAT[2]–FatalSP0_CTL_INDEP[6]
error
SP0_ERR_STAT[25]–Failed
Threshold
SP0_ERR_STAT[24]–
DegradedThreshold
Offset0x14004
SP0_CTL_INDEP[20]–Illegal
Transaction
SP0_CTL_INDEP[16]–Max
RetryError
Port1ErrorWrite1toclear:Write1toclearanyoftheWrite1toclear:
followingpossiblebits:
Offset0x0278Offset0x2080Offset0x14104
ERR_RST_EVNT_ICCR[9]SP1_ERR_STAT[2]–FatalSP1_CTL_INDEP[6]
error
SP1_ERR_STAT[25]–Failed
Threshold
SP1_ERR_STAT[24]–
DegradedThreshold
Offset0x14104
SP1_CTL_INDEP[20]–Illegal
Transaction
SP1_CTL_INDEP[16]–Max
RetryError
Port2ErrorWrite1toclear:Write1toclearanyoftheWrite1toclear:
(TMS320TCI6482Only)followingpossiblebits:
Offset0x0278Offset0x20C0Offset0x14204
ERR_RST_EVNT_ICCR[10]SP2_ERR_STAT[2]–FatalSP2_CTL_INDEP[6]
error
SP2_ERR_STAT[25]–Failed
Threshold
SP2_ERR_STAT[24]–
DegradedThreshold
Offset0x14204
SP2_CTL_INDEP[20]–Illegal
Transaction
SP2_CTL_INDEP[16]–Max
RetryError
SerialRapidIO(SRIO) 92SPRUE13A–September2006
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