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4.4InterruptConditionRoutingRegisters
4.4.1DoorbellInterruptConditionRoutingRegisters
InterruptConditions
Table38.InterruptClearingSequenceforSpecialEventInterrupts(continued)
InterruptFunction1
st
Step2
nd
Step3
rd
Step
Port3ErrorWrite1toclear:Write1toclearanyoftheWrite1toclear:
(TMS320TCI6482Only)followingpossiblebits:
Offset0x0278Offset0x2100Offset0x14304
ERR_RST_EVNT_ICCR[11]SP3_ERR_STAT[2]–FatalSP_CTL_INDEP[6]
error
SP3_ERR_STAT[25]–Failed
Threshold
SP3_ERR_STAT[24]–
DegradedThreshold
Offset0x14304
SP3_CTL_INDEP[20]–Illegal
Transaction
SP3_CTL_INDEP[16]–Max
RetryError
DeviceResetWrite1toclear:Write1toclear:
Offset0x0278Offset0x12004
ERR_RST_EVNT_ICCR[16]SP_IP_MODE[2]
Theinterruptconditionsareprogrammabletoselecttheinterruptoutputthatwillbedriven.Usingthe
interruptconditionroutingregisters(ICRRs),softwarecanindependentlyrouteeachinterruptrequestto
anyoftheinterruptdestinationssupportedbythedevice.Forexample,aquadcoredevicemaysupport
fourCPUservicinginterruptdestinations,onepercore(INTDST0forCore0,INTDST1forCore1,
INTDST2forCore2,andINTDST3forCore3).Inaddition,INTDST4maybegloballyroutedtoallcores
andprovidenotificationofachangeintheoneICSR,whileINTDST5maybegloballyroutedtoallcores
andprovidenotificationofachangeinadifferentICSR.Theroutingdefaultsforaninterruptcondition
routingbit(ICRx)aregiveninTable39.
Table39.InterruptConditionRoutingOptions
FieldAccessResetValueValueFunction
ICRxR0000b0000bRoutedtoINTDST0
0001bRoutedtoINTDST1
0010bRoutedtoINTDST2
0011bRoutedtoINTDST3
0100bRoutedtoINTDST4
0101bRoutedtoINTDST5
0110bRoutedtoINTDST6
0111bRoutedtoINTDST7
1111bNointerruptdestination,interruptsourcedisabled
otherReserved
Figure54showstheinterruptconditionroutingregistersforDoorbell0.TheotherdoorbellICRRshavethe
samebitfieldmap,withthefollowingaddresses:
•DOORBELL1_ICRRandDOORBELL1_ICCR2(Addressoffsets0290hand0294h)
•DOORBELL2_ICRRandDOORBELL2_ICRR2(Addressoffset02A0hand02A4h)
•DOORBELL3_ICRRandDOORBELL3_ICRR2(Addressoffset02B0hand02B4h)
SPRUE13A–September2006SerialRapidIO(SRIO)93
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