Texas Instruments TMS320TCI648x Network Card User Manual


 
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4.3InterruptConditionStatusandClearRegisters
InterruptConditions
TheDOORBELLpacket’s16-bitINFOfieldindicateswhichDOORBELLregisterinterruptbittoset.There
arefourDOORBELLregisters,eachcurrentlywith16bits,allowing64interruptsourcesorcircularbuffers
(seeTable23forassignmentofthe16bitsofDOORBELL_INFOfield).Eachbitcanbeassignedtoany
coreasdescribedbytheInterruptConditionRoutingRegisters.Additionally,eachstatusbitis
user-definedfortheapplication.Forinstance,itmaybedesirabletosupportmultipleprioritieswithmultiple
TIDcircularbufferspercoreifcontroldatausesahighpriority(forexample,priority=2),whiledata
packetsaresentonpriority0or1.Thisallowsthecontrolpacketstohavepreferenceintheswitchfabric
andarriveasquicklyaspossible.SinceitmayberequiredtointerrupttheCPUforbothdataandcontrol
packetprocessingseparately,separatecircularbuffersareused,andDOORBELLpacketsmust
distinguishbetweenthemforinterruptservicing.IfanyreservedbitintheDOORBELLinfofieldisset,an
errorresponseissent.
Theinterruptapproachtothemessagingprotocolissomewhatdifferent.Sincethesourcedeviceis
unawareofthedata'sphysicallocationinthedestinationdevice,andsinceeachmessagingpacket
containssizeandsegmentinformation,theperipheralcanautomaticallygeneratetheinterruptafterithas
successfullyreceivedallpacketsegmentscomprisingthecompletemessage.ThisDMAinterfaceuses
theCommunicationsPortProgrammingInterface(CPPI).Thisinterfaceisalink-listedapproachversusa
circularbufferapproach.DatabufferdescriptorswhichcontaininformationsuchasstartofPacket(SOP),
endofpacket(EOP),endofqueue(EOQ),andpacketlengtharebuiltfromtheRapidIOheaderfields.
Thedatabufferdescriptorsalsocontaintheaddressofthecorrespondingdatabufferasassignedbythe
receivedevice.Thedatabufferdescriptorsarethenlink-listedtogetherasmultiplepacketsarereceived.
Interruptsaregeneratedbytheperipheralafterallsegmentsofthemessagesarereceivedand
successfullytransferredthroughtheDMAbuswiththewrite-with-responsecommands.Interruptpacingis
alsoimplementedattheperipheralleveltomanagetheinterruptrate,asdescribedinSection4.7.
ErrorhandlingontheRapidIOlinkishandledbytheperipheral,andassuch,doesnotrequirethe
interventionofsoftwareforrecovery.ThisincludesCRCerrorsduetobitrateerrorsthatmaycause
erroneousorinvalidoperations.TheexceptiontothisstatementistheuseoftheRapidIOerror
managementextendedfeatures.Thisspecificationmonitorsandtabulatestheerrorsthatoccuronaper
portbasis.Ifthenumberoferrorsexceedsapre-determinedconfigurableamount,theperipheralshould
interrupttheCPUsoftwareandnotifythatanerrorconditionexits.Alternatively,ifasystemhostisused,
theperipheralmayissueaport-writeoperationtonotifythesystemsoftwareofabadlink.
Asystemreset,orCriticalErrorinterrupt,canbeinitializedthroughtheRapidIOlink.Thisprocedure
allowsanexternaldevicetoresetthelocaldevice,causingallstatemachineandconfigurationregistersto
resettotheiroriginalvalues.ThisisexecutedwiththeReset-DevicecommanddescribedinPartVI,
Section3.4.5oftheRapidIOPhysicalLayer1x/4xLP-SerialSpecification.FoursequentialReset-Device
controlsymbolsareneededtoavoidinadvertentresettingofadevice.
InterruptconditionstatusandclearregistersconfigurewhichCPUinterruptsaretobegeneratedandhow,
basedontheperipheralactivity.AllperipheralconditionsthatresultinaCPUinterruptaregroupedsothat
theinterruptcanbeaccessedintheminimumnumberofregisterreadspossible.
Foreachofthethreetypesofinterrupts(CPUservicing,errorstatus,andcriticalerror),therearetwosets
ofregisters:
InterruptConditionStatusRegister(ICSR):Statusregisterthatreflectsthestateofeachconditionthat
cantriggertheinterrupt.Thegeneraldescriptionofeachinterruptconditionstatusbit(ICSx)isgivenin
Table35.
InterruptConditionClearRegister(ICCR):Commandregisterthatallowseachconditiontobecleared.
Thisistypicallyrequiredpriortoenablingacondition,sothatspuriousinterruptsarenotgenerated.
Table35showsthegeneraldescriptionofaninterruptconditionclearbit(ICCx).
TheseregistersareaccessibleinthememorymapoftheCPU.TheCPUcontrolstheclearregister.The
statusregisterisreadablebytheCPUtodeterminetheperipheralcondition.
SerialRapidIO(SRIO) 86SPRUE13ASeptember2006
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