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5.93PortIPPrescalerRegister(IP_PRESCAL)
SRIORegisters
TheportIPprescalerregister(IP_PRESCAL)isshowninFigure156anddescribedinTable178.This
registerdefinesaprescalerfordifferentfrequenciesoftheDMAclock.Thepurposeofthisregisteristo
keepthetimersofSP_LT_CTL(offset01120h),SP0_ERR_RATEthroughSP3_ERR_RATE(offsets
02068h,020A8h,020E8,and02128h),SP_IP_DISCOVERY_TIMER(offset12000h),and
SP0_SILENCE_TIMERthroughSP3_SILENCE_TIMER(offsets14008h,14108h,14208h,and14308h)
withinthesamerangefordifferentfrequenciesoftheDMAclock.
Figure156.PortIPPrescalerRegister(IP_PRESCAL)-AddressOffset12008h
3116
Reserved
R-0000h
15870
ReservedPRESCALE
R-00hRW-0Fh
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table178.PortIPPrescalerRegister(IP_PRESCAL)FieldDescriptions
BitFieldValueDescription
31–8Reserved000000hTheseread-onlybitsreturn0swhenread.
7–0PRESCALEFordifferentfrequenciesoftheDMAclock,usethefollowingformulatogettheprescalervaluein
decimal,wheretheDMAclockfrequencyisinMHz:
DMAclockfrequencyx16
156.25–1
06h66.67MHz
......
09h100MHz
......
0Fh156.25MHz
10h166.67MHz
......
18h250MHz
...
21h333MHz
SPRUE13A–September2006SerialRapidIO(SRIO)233
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