Texas Instruments TMS320TCI648x Network Card User Manual


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2.3.9.1TranslationforMMRspace
A0
A0
A2
A2
A1
A1
A3
A3
L2offset0x0
DSP definedMMR
offset0x1000
Byte
lane0
31
Byte
lane3
DMA 32b
0
2.3.9.2EndianConversion(TMS320TCI6482)
RapidIOdefinedbitpositions
A0 A1 A2 A3
310
MMRoffset0x0000
B0 B1 B2 B3
MMRoffset0x0004
C0
C1 C2 C3
MMRoffset0x0008
D0
D1 D2 D3
MMRoffset0x000C
RapidIO
defined
MMR
offsets
A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3
Headerfields
Type8
Response
A0
A1 A2 A3
Byte
address3
Byte
Byte
address0
L2offset0x0
B0 B1 B2 B3
L2offset0x4
C0 C1 C2 C3
L2offset0x8
D0
D1 D2 D3
L2offset0xC
BigEndian
LittleEndian
A3
A2 A1 A0
Byte
address0address3
L2offset0x0
B3 B2 B1 B0
L2offset0x4
C3 C2 C1 C0
L2offset0x8
D3
D2 D1 D0
L2offset0xC
Double-word0 Double-word1
ThedesiredoperationistosendaType8maintenancerequesttoanexternaldevice.
Thegoalistoread16BofRapidIOMMR fromanexternaldevice,startingoffset0x0000.
ThisoperationinvolvestheLSUblockandutilizestheDMA fortransferringtheresponse
packetpayload.
SRIOFunctionalDescription
TherearenoEndiantranslationrequirementsforaccessingthelocalMMRspace.Regardlessofthe
devicememoryEndianconfiguration,allconfigurationbusaccessesareperformedon32-bitvaluesata
fixedaddressposition.Thebitpositionsinthe32-bitwordaredefinedbythisspecification.Thismeans
thatamemoryimagewhichwillbecopiedtoaMMRisidenticalbetweenLittleEndianandBigEndian
configurations.Configurationbusreadsareperformedinthesamemanner.Figure30illustratesthe
concept.ThedesiredoperationistolocallyupdateaserialRapidIOMMR(offset1000h)withavalueof
A0A1A2A3h,usingtheconfigurationbus.
Figure30.ConfigurationBusExample
WhenaccessingRapidIOdefinedMMRwithinanexternaldevice,RapidIOallows4bytes,8bytes,orany
multipleofadouble-wordaccess(upto64bytes)fortype8(maintenance)packets.Theperipheralonly
supports4-byteaccessesasthetarget,butcangenerateallsizesofrequestpackets.RapidIOisdefined
asBigEndianonly,andhasdouble-wordalignedBigEndianpacketpayloads.
TheDMA,however,supportsbytewideaccesses.TheperipheralperformsEndianconversiononthe
payloadifLittleEndianisusedonthedevice.Thisconversionisnotonlyapplicablefortype8packets,but
isalsorelevantforalloutgoingpayloadsofNWRITE,NWRITE_R,SWRITE,NREAD,andmessage
packets.ThismeansthatthememoryimageisdifferentbetweenLittleEndianandBigEndian
configurations,asshowninFigure31.
Figure31.DMAExample
SPRUE13A–September2006SerialRapidIO(SRIO)69
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