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5.5PeripheralGlobalEnableRegister(GBL_EN)
SRIORegisters
GBL_ENisimplementedwithasingleenablebitfortheentireSRIOperipheral.ThisbitislogicallyORed
withtheresetinputtothemoduleandisfannedouttoalllogicalblockswithintheperipheral.GBL_ENis
showninFigure66anddescribedinTable44.Foradditionalprogramminginformation,see
Section2.3.10.
Figure66.PeripheralGlobalEnableRegister(GBL_EN)(AddressOffset0030h)
3110
ReservedEN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table44.PeripheralGlobalEnableRegister(GBL_EN)FieldDescriptions
BitFieldValueDescription
31–1Reserved00000000hTheseread-onlybitsreturn0swhenread.
0ENGlobalenable.Thisbitcontrolsresettoallclockdomainswithintheperipheral.
0Theperipheralistobedisabled(heldinresetwithclocksdisabled).
1Theperipheralistobeenabled.
SerialRapidIO(SRIO) 116SPRUE13A–September2006
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