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2.3.4.3ResetandPowerDownState
SRIOFunctionalDescription
AtransactiontimeoutisusedbyalloutgoingmessageanddirectI/Opackets.Ithasthesamevalueandis
analogoustotherequest-to-responsetimerdiscussedintheRXCPPIandLSUsections,whichisdefined
bythe24-bitvalueintheportresponsetime-outCSR(SeeSection2.3.3.3).TheRapidIOInterconnect
Specificationstatesthatthemaximumtimeinterval(all1s)isbetween3and6seconds.Alogicallayer
timeoutoccursiftheresponsepacketisnotreceivedbeforeacountdowntimer(initializedtothisCSR
value)reacheszero.Sincetransactionresponsescanbeacknowledgedout-of-order,atimerisneededfor
eachsupportedoutstandingpacketintheTXqueue.Eachoutstandingpacketresponsetimerrequiresa
4-bitregister.Theregisterisloadedwiththecurrenttimecodewhenthetransactionissent.Eachtimethe
timecodechanges,a4-bitcompareisdonetothe16outstandingpacketregisters.Iftheregisterbecomes
equaltothetimecodeagain,withoutaresponsebeingseen,thenthetransactionhastimedoutandthe
bufferdescriptoriswritten.
Essentially,insteadofthe24-bitvaluerepresentingtheperiodoftheresponsetimer,theperiodisnow
definedasP=(2
24
x16)/F.Thismeansthecountdowntimerfrequencyneedstobe44.7–89.5MHzfora
6–3secondresponsetimeout.SincetheneededtimerfrequencyisderivedfromtheDMAbusclock
(whichisdevicedependent),thehardwaresupportsaprogrammableconfigurationregisterfieldto
properlyscaletheclockfrequency.ThisconfigurationregisterfieldisdescribedinthePeripheralSetting
Controlregister(Addressoffset0020h).
TheCPUinitiatesaTXqueueteardownbywritingtotheTXQueueTeardowncommandregister.
TeardownofaTXqueuewillcausethefollowingactions:
•Nonewmessageswillbesent.
•Allmessages(singleandmulti-segment)alreadystartedwillbecompleted.
–FailingtocompletethemessageTXwouldleaveanactivereceiverblockedwaitingforthefinal
segmentsuntilthetransactioneventuallytimes-out.
–NotethatnormalTXStateMachineoperationistonotsendanymoresegmentsonceanerror
responsehasbeenreceivedonanysegment.Soifthereceiverhasalsobeentorn-down(andis
receivingerrorresponses)multi-segmenttransmitwillcompleteassoonasallin-transitsegments
havebeenrespondedto.
•Whenallin-transitmessages/segmentshavebeenrespondedto,teardownwillbecompletedas
follows:
–Ifthequeueisactive,theteardownbitwillbesetinthenextbufferdescriptorinthequeue.The
peripheralcompletestheteardownprocedurebyclearingtheHDPregister,settingtheCPregister
toFFFFFFFCh,andissuinganinterruptforthegivenqueue.Theteardowncommandregisterbitis
automaticallyclearedbytheperipheral.
–Ifthequeueisin-active(noadditionalbufferdescriptorsavailable),orbecomesinactiveaftera
messageintransmissioniscompleted,nobufferdescriptorfieldsarewritten.TheHDPregisterand
theCPregisterremainunchanged.Aninterruptisnotissued.Theteardowncommandregisterbit
isautomaticallyclearedbytheperipheral.
–Becauseoftopologydifferencesbetweenflow'sresponse,packetsmayarriveinadifferentorderto
theorderofrequests.
AftertheteardownprocessiscompleteandtheinterruptisservicedbytheCPU,softwaremust
re-initializetheTXqueuetorestartnormaloperation.
Uponreset,theCPPImodulemustbeconfiguredbytheCPU.TheCPUsetsupthereceiveandtransmit
queuesinmemory.ThentheCPUupdatestheCPPImodulewiththeappropriateRX/TXDMAstatehead
descriptorpointer,sotheperipheralknowswithwhichbufferdescriptoraddresstostart.Additionally,the
CPUmustprovidetheCPPImodulewithinitialbufferdescriptorvaluesforeachdatabuffer.
TheCPPImodulecanbepowereddownifthemessagepassingprotocolisnotbeingsupportedinthe
application.Forexample,ifthedirectI/Oprotocolisbeingusedfordatatransfers,poweringdownthe
CPPImodulewillsavepower.Inthissituation,thebufferdescriptorqueueSRAMsandmailboxmapper
logicshouldbepowereddown.Clocksshouldbegatedtotheseblockswhileinthepowerdownstate.
Section2.3.10describesthisindetail.
SPRUE13A–September2006SerialRapidIO(SRIO)59
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