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Port0
8x276 TX
8x276RX
8x276RX
8x276 TX
Port1
8x276 TX
8x276RX
Port2
8x276RX
8x276 TX
Port3
Physical
layer
buffers
SERDES0 SERDES1 SERDES2 SERDES3
SERDES
differential
signals
4xmode
datapath
TXbuffering
32x276B
8buffersper1Xport-allpriorities
32buffersper4Xport-8perpriority
Transaction
mapping
layer
buffers
Logical
Load/Store
units(LSUs)
TXdirectI/O
Maintenance
Messaging
TXU
RXdirectI/O
(MAU)
Memory
accessunit
RXU
Messaging
buffer
4.5KB TX
shared
buffer
shared
4.5KBRX
handle
Queue
DMA bus
UDI
SRIOFunctionalDescription
Figure8.SRIOComponentBlockDiagram
SPRUE13A–September2006SerialRapidIO(SRIO)27
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