Texas Instruments TMS320TCI648x Network Card User Manual


 
www.ti.com
5.66PortLinkTime-OutControlCSR(SP_LT_CTL)
SRIORegisters
Theportlinktime-outcontrolCSR(SP_LT_CTL)isshowninFigure129anddescribedinTable137.
Figure129.PortLinkTime-OutControlCSR(SP_LT_CTL)-AddressOffset1120h
31
TIMEOUT_VALUE
R/W-FFFFFFh
870
TIMEOUT_VALUEReserved
R/W-FFFFFFhR-00h
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table137.PortLinkTimeoutControlCSR(SP_LT_CTL)FieldDescriptions
BitFieldValueDescription
31–8TIMEOUT_VALUETimeoutvalueforallportsonthedevice.Thistimeoutisforlinkevents
suchassendingapackettoreceivingthecorrespondingACK.Max
valuerepresents3-6seconds.Timeoutduration=205ns*Timeout
Value;whereTimeoutvalueisthedecimalrepresentationofthisregister
value.
FFFFFFh3.4s
0FFFFFh215ms
00FFFFh13.4ms
000FFFh839.5µs
0000FFh52.3µs
00000Fh3.1µs
000001h205nsforsimulationonly
000000hTimerdisabled
7–0Reserved00hTheseread-onlybitsreturn0swhenread.
SPRUE13ASeptember2006SerialRapidIO(SRIO)197
SubmitDocumentationFeedback