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5.42QueuenTransmitDMACompletionPointerRegister(QUEUEn_TXDMA_CP)
SRIORegisters
Therearesixteenoftheseregisters(seeTable106).QUEUEn_TXDMA_CPisshowninFigure104and
describedinTable107.Foradditionalprogramminginformation,seeSection2.3.4.2.
Table106.QUEUEn_TXDMA_CPRegisters
RegisterAddressOffset
QUEUE0_TXDMA_CP0580h
QUEUE1_TXDMA_CP0584h
QUEUE2_TXDMA_CP0588h
QUEUE3_TXDMA_CP058Ch
QUEUE4_TXDMA_CP0590h
QUEUE5_TXDMA_CP0594h
QUEUE6_TXDMA_CP0598h
QUEUE7_TXDMA_CP059Ch
QUEUE8_TXDMA_CP05A0h
QUEUE9_TXDMA_CP05A4h
QUEUE10_TXDMA_CP05A8h
QUEUE11_TXDMA_CP05ACh
QUEUE12_TXDMA_CP05B0h
QUEUE13_TXDMA_CP05B4h
QUEUE14_TXDMA_CP05B8h
QUEUE15_TXDMA_CP05BCh
Figure104.QueuenTransmitDMACompletionPointerRegister(QUEUEn_TXDMA_CP)
310
TX_CP
R/W-00000000h
LEGEND:R/W=Read/Write;-n=Valueafterreset
Table107.QueueTransmitDMACompletionPointerRegisters(QUEUEn_TXDMA_CP)Field
Descriptions
BitFieldValueDescription
31–0TX_CP00000000hThisfieldisthememoryaddressforthetransmitqueuecompletionpointer.This
toregisteriswrittenbytheDSPcorewiththebufferdescriptoraddressforthelast
FFFFFFFFhbufferprocessedbythehostduringinterruptprocessing.Theportusesthevalue
writtentodetermineiftheinterruptshouldbedeasserted.
SPRUE13A–September2006SerialRapidIO(SRIO)165
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