Filter
Top Products
ListofFigures
1RapidIOArchitecturalHierarchy..........................................................................................17
2RapidIOInterconnectArchitecture.......................................................................................18
3SerialRapidIODevicetoDeviceInterfaceDiagrams.................................................................19
4SRIOPeripheralBlockDiagram..........................................................................................22
5OperationSequence.......................................................................................................23
61x/4xRapidIOPacketDataStream(Streaming-WriteClass)........................................................24
7SerialRapidIOControlSymbolFormat..................................................................................24
8SRIOComponentBlockDiagram........................................................................................27
9SERDESMacroConfigurationRegister0(SERDES_CFG0_CNTL)...............................................28
10SERDESReceiveChannelConfigurationRegistern(SERDES_CFGRXn_CNTL)...............................31
11SERDESTransmitChannelConfigurationRegistern(SERDES_CFGTXn_CNTL)..............................33
12Load/StoreRegistersforRapidIO(AddressOffset:LSU1400h–418h,LSU2420h–438h,LSU3
440h–458h,LSU4460h-478h)...........................................................................................36
13LSURegistersTiming.....................................................................................................38
14ExampleBurstNWRITE_R...............................................................................................39
15Load/StoreModuleDataFlowDiagram.................................................................................40
16CPPIRXSchemeforRapidIO............................................................................................44
17MessageRequestPacket.................................................................................................45
18MailboxtoQueueMappingRegisterPair...............................................................................46
19RXBufferDescriptorFields...............................................................................................47
20RXCPPIModeExplanation..............................................................................................49
21CPPIBoundaryDiagram..................................................................................................51
22TXBufferDescriptorFields...............................................................................................52
23WeightedRoundRobinProgrammingRegisters(AddressOffset7E0h–7ECh)...................................56
24RXBufferDescriptors......................................................................................................62
25TXBufferDescriptors......................................................................................................63
26DoorbellOperation.........................................................................................................64
27FlowControlTableEntryRegisters(AddressOffset0900h–093Ch)...............................................66
28TransmitSourceFlowControlMasks...................................................................................67
29FieldsWithinEachFlowMask............................................................................................67
30ConfigurationBusExample...............................................................................................69
31DMAExample..............................................................................................................69
32GBL_EN(Address0030h)................................................................................................71
33GBL_EN_STAT(Address0034h)........................................................................................71
34BLK0_EN(Address0038h)...............................................................................................72
35BLK0_EN_STAT(Address003Ch)......................................................................................73
36BLK1_EN(Address0040h)...............................................................................................73
37BLK1_EN_STAT(Address0044h).......................................................................................73
38BLK8_EN(Address0078h)...............................................................................................73
39BLK8_EN_STAT(Address007Ch)......................................................................................73
40PeripheralControlRegister(PCR)-AddressOffset0004h..........................................................74
41BootloadOperation........................................................................................................80
42PacketForwardingRegisternfor16-BitDeviceIDs(PF_16B_CNTLn)Offsets0x0090,0x0098,0x00A0,
0x00A8.......................................................................................................................81
43PacketForwardingRegisternfor8-BitDeviceIDs(PF_8B_CNTLn)Offsets0x0094,0x009C,0x00A4,
0x00AC......................................................................................................................82
44Logical/TransportLayerErrorDetectCSR(ERR_DET)..............................................................83
45RapidIODOORBELLPacketforInterruptUse.........................................................................85
46Doorbell0InterruptConditionStatusandClearRegisters...........................................................87
47Doorbell1InterruptConditionStatusandClearRegisters...........................................................87
48Doorbell2InterruptConditionStatusandClearRegisters...........................................................88
49Doorbell3InterruptConditionStatusandClearRegisters...........................................................88
6ListofFiguresSPRUE13A–September2006
SubmitDocumentationFeedback