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5.21TXCPPIInterruptClearRegister(TX_CPPI_ICCR)
SRIORegisters
ThisregisterisusedtoclearbitsinTX_CPPI_ICSRtoacknowledgeinterruptsfromtheTXbuffer
descriptorqueues.TX_CPPI_ICCRisshowninFigure82anddescribedinTable72.
Figure82.TXCPPIInterruptConditionClearRegister(TX_CPPI_ICCR)-AddressOffset0258h
3116
Reserved
R-0
1514131211109876543210
ICC15ICC14ICC13ICC12ICC11ICC10ICC9ICC8ICC7ICC6ICC5ICC4ICC3ICC2ICC1ICC0
W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0
LEGEND:R=Readonly;W=Writeonly;-n=Valueafterreset
Table72.TXCPPIInterruptConditionClearRegister(TX_CPPI_ICCR)FieldDescriptions
BitFieldValueDescription
31–16Reserved0Theseread-onlybitsreturn0whenread.
15–0ICCxTXCPPIinterruptclear
(x=15to0)
0Noeffect
1ClearbitxofTX_CPPI_ICSR.
SPRUE13A–September2006SerialRapidIO(SRIO)137
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