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SRIOFunctionalDescription
Table9.SERDESReceiveChannelConfigurationRegistern(SERDES_CFGRXn_CNTL)Field
Descriptions(continued)
BitFieldValueDescription
25–24Reserved00bAlwayswrite0stothesereservedbits.
23Reserved0Thisread-onlybitreturns0whenread.
22–19EQ0000b–1111bEqualizer.Enablesandconfigurestheadaptiveequalizertocompensateforloss
inthetransmissionmedia.Fortheselectablevalues,seeTable10.
18–16CDRClock/datarecovery.Configurestheclock/datarecoveryalgorithm.
000bFirstorder.Phaseoffsettrackingupto±488ppm.
001bSecondorder.Highestprecisionfrequencyoffsetmatchingbutpoorestresponse
tochangesinfrequencyoffset,andlongestlocktime.Suitableforuseinsystems
withfixedfrequencyoffset.
010bSecondorder.Mediumprecisionfrequencyoffsetmatching,frequencyoffset
changeresponse,andlocktime.
011bSecondorder.Bestresponsetochangesinfrequencyoffsetandfastestlocktime,
butlowestprecisionfrequencyoffsetmatching.Suitableforuseinsystemswith
spreadspectrumclocking.
100bFirstorderwithfastlock.Phaseoffsettrackingupto±1953ppminthepresenceof
..10101010..trainingpattern,and±448ppmotherwise.
101bSecondorderwithfastlock.Aspersetting001,butwithimprovedresponseto
changesinfrequencyoffsetwhennotclosetolock.
110bSecondorderwithfastlock.Aspersetting010,butwithimprovedresponseto
changesinfrequencyoffsetwhennotclosetolock.
111bSecondorderwithfastlock.Aspersetting011,butwithimprovedresponseto
changesinfrequencyoffsetwhennotclosetolock.
15–14LOSLossofsignal.Enableslossofsignaldetectionwith2selectablethresholds.
00bDisabled.Lossofsignaldetectiondisabled.
01bHighthreshold.Lossofsignaldetectionthresholdintherange85to195mV
dfpp
.
ThissettingissuitableforInfiniband.
10bLowthreshold.Lossofsignaldetectionthresholdintherange65to175mV
dfpp
.
ThissettingissuitableforPCI-EandS-ATA.
11bReserved
13–12ALIGNSymbolalignment.Enablesinternalorexternalsymbolalignment.
00bAlignmentdisabled.Nosymbolalignmentwillbeperformedwhilethissettingis
selected,orwhenswitchingtothisselectionfromanother.
01bCommaalignmentenabled.Symbolalignmentwillbeperformedwhenevera
misalignedcommasymbolisreceived.
10bAlignmentjog.Thesymbolalignmentwillbeadjustedbyonebitpositionwhenthis
modeisselected(thatis,theALIGNvaluechangesfrom0xbto1xb).
11bReserved
11Reserved0Thisread-onlybitreturns0whenread.
10–8TERM001bInputtermination.Theonlyvalidvalueforthisfieldis001b;allothervaluesare
reserved.Thevalue001bsetsthecommonpointto0.8VDDTandsupportsAC
coupledsystemsusingCMLtransmitters.Thetransmitterhasnoeffectonthe
receivercommonmode,whichissettooptimizetheinputsensitivityofthe
receiver.Commonmodeterminationisviaa50pFcapacitortoVSSA.
7INVPAIRInvertpolarity.InvertspolarityofRIORXnandRIORXn.
0Normalpolarity.RIORXnisconsideredtobepositivedataandRIORXnnegative.
1Invertedpolarity.RIORXnisconsideredtobenegativedataandRIORXnpositive.
6–5RATEOperatingrate.Selectsfull,half,orquarterrateoperation.
00bFullrate.TwodatasamplestakenperPLLoutputclockcycle.
01bHalfrate.OnedatasampletakenperPLLoutputclockcycle.
10bQuarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11bReserved
32SerialRapidIO(SRIO)SPRUE13A–September2006
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