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2.3.2.3EnablingtheTransmitter
SRIOFunctionalDescription
Table9.SERDESReceiveChannelConfigurationRegistern(SERDES_CFGRXn_CNTL)Field
Descriptions(continued)
BitFieldValueDescription
4–2BUSWIDTH000bBuswidth.Alwayswrite000btothisfield,toindicatea10-bit-wideparallelbusto
theclock.Allothervaluesarereserved.SeeSection2.3.2.1foranexplanationof
thebus.
1Reserved0Alwayswrite0tothisreservedbit.
0ENRXEnablereceiver
0Disablethisreceiver.
1Enablethisreceiver.
Table10.EQBits
CFGRX[22–19]LowFreqGainZeroFreq(ate
28
(min))
0000bMaximum–
0001bAdaptiveAdaptive
001xbReserved
01xxbReserved
1000bAdaptive1084MHz
1001b805MHz
1010b573MHz
1011b402MHz
1100b304MHz
1101b216MHz
1110b156MHz
1111b135MHz
Toenableatransmitterforserialization,theENTXbitoftheassociatedSERDES_CFGTXn_CNTL
registers(110h–10Ch)mustbesethigh.WhenENTXislow,alldigitalcircuitrywithinthetransmitterwill
bedisabled,andclockswillbegatedoff,withtheexceptionofthetransmitclock(TXBCLK[n])output,
whichwillcontinuetooperatenormally.Allcurrentsourceswithinthetransmitterwillbefullypowered
down,withtheexceptionofthecurrentmodelogic(CML)driver,whichwillremainpoweredupifboundary
scanisselected.Figure11showsthefieldsofSERDES_CFGTXn_CNTLandTable11describesthem.
Figure11.SERDESTransmitChannelConfigurationRegistern(SERDES_CFGTXn_CNTL)
311716
ReservedENFTP
R-0R/W-1
151211987654210
DESWINGCMINVPAIRRATEBUSWIDTH(write0)ENTX
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table11.SERDESTransmitChannelConfigurationRegistern(SERDES_CFGTXn_CNTL)Field
Descriptions
BitFieldValueDescription
31–17Reserved0Theseread-onlybitsreturn0swhenread.
16ENFTP1Enablesfixedphaserelationshipoftransmitinputclockwithrespecttotransmitoutput
clock.Theonlyvalidvalueforthisfieldis1b;allothervaluesarereserved.
SPRUE13A–September2006SerialRapidIO(SRIO)33
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