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5.43QueuenReceiveDMAHeadDescriptorPointerRegister(QUEUEn_RXDMA_HDP)
SRIORegisters
Therearesixteenoftheseregisters(seeTable108).QUEUEn_RXDMA_HDPisshowninFigure105and
describedinTable109.Foradditionalprogramminginformation,seeSection2.3.4.1.
Table108.QUEUEn_RXDMA_HDPRegisters
RegisterAddressOffset
QUEUE0_RXDMA_HDP0600h
QUEUE1_RXDMA_HDP0604h
QUEUE2_RXDMA_HDP0608h
QUEUE3_RXDMA_HDP060Ch
QUEUE4_RXDMA_HDP0610h
QUEUE5_RXDMA_HDP0614h
QUEUE6_RXDMA_HDP0618h
QUEUE7_RXDMA_HDP061Ch
QUEUE8_RXDMA_HDP0620h
QUEUE9_RXDMA_HDP0624h
QUEUE10_RXDMA_HDP0628h
QUEUE11_RXDMA_HDP062Ch
QUEUE12_RXDMA_HDP0630h
QUEUE13_RXDMA_HDP0634h
QUEUE14_RXDMA_HDP0638h
QUEUE15_RXDMA_HDP063Ch
Figure105.QueuenReceiveDMAHeadDescriptorPointerRegister(QUEUEn_RXDMA_HDP)
310
RX_HDP
R/W-00000000h
LEGEND:R/W=Read/Write;-n=Valueafterreset
Table109.QueuenReceiveDMAHeadDescriptorPointerRegister(QUEUEn_RXDMA_HDP)Field
Descriptions
BitFieldValueDescription
31–0RX_HDP00000000hRXQueueHeadDescriptorPointer:Thisfieldisthememoryaddressforthefirst
tobufferdescriptorinthechannelreceivequeue.ThisfieldiswrittenbytheDSP
FFFFFFFChcoretoinitiatequeuereceiveoperationsandiszeroedbytheportwhenallfree
buffershavebeenused.AnerrorconditionresultsiftheDSPcorewritesthis
fieldwhenthecurrentfieldvalueisnonzero.Theaddressmustbe32-bitword
aligned(the2LSBsmustbe0s).
SerialRapidIO(SRIO) 166SPRUE13A–September2006
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