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2.3.12TXBuffers,Credit,andPacketReordering
2.3.12.1MultiplePortsWith1xOperation
SRIOFunctionalDescription
Table29.PeripheralControlRegister(PCR)FieldDescriptions(continued)
BitFieldValueDescription
1SOFTSoftstop.ThisbitandtheFREEbitdeterminehowtheSRIOperipheralbehavesduringemulation
halts.
0Hardstop.Allstatusregistersarefrozenindefaultstate.(ThismodeisnotsupportedontheSRIO
peripheral.)
1Softstop
0FREEFreerun
0TheSOFTbittakeseffect.
1Freerun.Peripheralignorestheemulationsuspendsignalandfunctionsnormally.
FreeRunMode:(defaultmode)Peripheraldoesnotrespondtoanemulationsuspendassertion.The
peripheralfunctionsnormally,irrespectiveoftheCPUemulationstate.
SoftStopMode:Theperipheralgracefullyhaltsoperations.Theperipheralhaltsoperationatapointthat
makessensebothtotheinternalDMA/dataaccessoperationandtothepininterfaceasdescribedbelow,
afterfinishingpacketreceptionortransmissioninprogress:
•DMAbusDMAmaster:DMAbusrequestsinprogressareallowedtocomplete(DMAbushasno
meanstothrottlecommandinprogressfromthemaster).DMAbusrequeststhatcorrespondtothe
samenetworkpacketareallowedtocomplete.NonewDMAbusrequestswillbegeneratedonthe
nextnewpacket.
•ConfigurationbusMMRinterface:Allmemory-mappedregister(MMR)configurationbusrequests
areservicedasnormal.
•Events/interrupts:Newevents/interruptsarenotgeneratedtotheCPUfornewlyarrivingpackets.
Currenttransactionsareallowedtofinishandmaycauseaninterruptuponcompletion.
•Slavepininterface:Thepininterfacefunctionsasnormal.Ifbufferingisavailableintheperipheral,
theperipheralservicesexternallygeneratedrequestsaslongaspossible.Whentheinternalbuffers
areconsumed,theperipheralwillretryincomingnetworkpacketsinthephysicallayer.
•Masterpininterface:Nonewmasterrequestsaregenerated.Masterrequestsinprogressare
allowedtocomplete,includingallpacketslocatedinthephysicallayertransmitbuffers.
HardStopMode:Theperipheralhaltsimmediately.Thismodeisnotsupportedintheperipheral.
PacketstobetransmittedbytheSRIOperipheraltraveltologicallayerbuffers.Thepacketsarethen
movedfromthelogicallayerbufferstophysicallayerbuffers.Fromthephysicallayerbuffers,thepackets
aretransmittedthroughaporttoaconnecteddevice.
Withmultipleportsin1xmode,logicallayerbuffersaregroupedperportandcontainallpriorities.Each
groupis8buffersdeep.Acounterismaintainedforeachporttotrackavailablebuffercreditacrossthe
UDI.Thecountisinitializedto8creditsperport.Thecountisdecrementedeachtimeapacketissent
acrosstheUDIforaport.Eachportbuffergrouphasabufferreleasesignalwhichindicatesthereleaseof
apacketfromthelogicallayerbuffertotheport'sphysicalbuffer,thusindicatingthefreeingupofspacein
theport'slogicalbuffer.
Thresholdsareusedtogovernoutboundcreditwhenrequestedbytheprotocolunits(MAU,RXU,TXU,
andtheLSUs).Thesethresholdsareprogrammableintheperipheralsettingscontrolregister
(PER_SET_CNTLataddressoffset0020h).
ThephysicallayerbuffertriestoprocessallpacketsintheordertheyweresentacrosstheUDI.However,
itisalsogovernedbyare-orderingalgorithmtodecidewhichpacketsmaybesenttothephysicallayer
bufferdependingoncreditavailabilitythere.
SPRUE13A–September2006SerialRapidIO(SRIO)75
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