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5.8BlocknEnableStatusRegister(BLKn_EN_STAT)
SRIORegisters
Therearenineoftheseregisters,oneforeachofninelogicalblocksintheperipheral.Theregistersand
theblockstheysupportarelistedinTable48.Thegeneralformforablocknenablestatusregister
(BLKn_EN_STAT)isshowninFigure69anddescribedinTable49.Foradditionalprogramming
information,seeSection2.3.10.
Table48.BlocknEnableStatusRegistersandtheAssociatedBlocks
RegisterAddressOffsetAssociatedBlock
BLK0_EN_STAT003ChLogicalblock0:thesetofmemory-mappedcontrolregistersfortheSRIO
peripheral
BLK1_EN_STAT0044hLogicalblock1:theLoad/Storemodule(thefourLSUsandsupportinglogic)
BLK2_EN_STAT004ChLogicalblock2:thememoryaccessunit(MAU)
BLK3_EN_STAT0054hLogicalblock3:themessagetransmitunit(TXU)
BLK4_EN_STAT005ChLogicalblock4:themessagereceiveunit(RXU).
BLK5_EN_STAT0064hLogicalblock5:SRIOport0
BLK6_EN_STAT006ChLogicalblock6:SRIOport1.
BLK7_EN_STAT0074hLogicalblock7:SRIOport2.
BLK8_EN_STAT007ChLogicalblock8:SRIOport3.
Figure69.BlocknEnableStatusRegister(BLKn_EN)
3110
ReservedEN_STAT
R-0R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table49.BlocknEnableStatusRegister(BLKn_EN_STAT)FieldDescriptions
BitFieldValueDescription
31-1Reserved0Theseread-onlybitsreturn0swhenread.
0EN_STATBlocknenablestatus
0Logicalblocknisresetwithitsclockoff.
1Logicalblocknisenabledwithitsclockrunning.
SerialRapidIO(SRIO) 120SPRUE13A–September2006
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