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4.4.1.2LSUInterruptConditionRoutingRegisters
InterruptConditions
Figure56.TXCPPIInterruptConditionRoutingRegisters
TXCPPIInterruptConditionRoutingRegister(TX_CPPI_ICRR)(AddressOffset02D0h)
3128272423201916
ICR7ICR6ICR5ICR4
R/W-0000R/W-0000R/W-0000R/W-0000
15121187430
ICR3ICR2ICR1ICR0
R/W-0000R/W-0000R/W-0000R/W-0000
TXCPPIInterruptConditionRoutingRegister2(TX_CPPI_ICRR2)(AddressOffset02D4h)
3128272423201916
ICR15ICR14ICR13ICR12
R/W-0000R/W-0000R/W-0000R/W-0000
15121187430
ICR11ICR10ICR9ICR8
R/W-0000R/W-0000R/W-0000R/W-0000
LEGEND:R/W=Read/Write;-n=Valueafterreset
Figure57showstheICRRsfortheLSUinterruptrequests.TheseregistersrouteLSUinterruptrequeststo
interruptdestinations.Forexample,ifICS4=1inLSU_ICSRandICR4=0000binLSU_ICRR0,LSU1
hasgeneratedatransaction-timeoutinterruptrequest,andthatrequestisroutedtointerruptdestination0.
SPRUE13A–September2006SerialRapidIO(SRIO)95
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