Texas Instruments TMS320TCI648x Network Card User Manual


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1.25to3.125Gbps
differentialdata
RX
Clock
recovery
S2P
10b
Clk
8b/10b
decode
8b
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
RX
8b8b/10b
decode
10b
ClkS2P
PLL
TX
TX
TX
TX
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b
8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
andstatus
registers
SERDES
Clockdomain2
Clockdomain3
Clockdomain1
DMA
bus
PacketGeneration
Lanestriping
Lanede-skew
CRCerrordetection
CRCgeneration
Buf
feringaddressanddatahandoff
FIFO
FIFO
FIFO
FIFO
2.1.2SRIOPackets
2.1.2.1OperationSequence
SRIOFunctionalDescription
Figure4.SRIOPeripheralBlockDiagram
Withinthephysicallayer,thedatanextgoestothe8-bit/10-bit(8b/10b)decodeblock.8b/10bencodingis
usedbyRapidIOtoensureadequatedatatransitionsfortheclockrecoverycircuits.Herethe20%
encodingoverheadisremovedasthe10-bitdataisdecodedtotheraw8-bitdata.Atthispoint,the
recoveredbyteclockisstillbeingused.
Thenextstepisclocksynchronizationanddataalignment.ThesefunctionsarehandledbytheFIFOand
lanede-skewingblocks.IntheRapidIOInterconnectSpecification,a"lane"isoneserialdifferentialpair.
TheFIFOprovidesanelasticstoremechanismusedtohandoffbetweentherecoveredclockdomains
andacommonsystemclock.AftertheFIFO,thefourlanesaresynchronizedinfrequencyandphase,
whether1Xor4Xmodeisbeingused.TheFIFOis8wordsdeep.Thelanede-skewisonlymeaningfulin
the4Xmode,whereitalignseachchannel’swordboundaries,suchthattheresulting32-bitwordis
correctlyaligned.
TheCRCerrordetectionblockkeepsarunningtallyoftheincomingdataandcomputestheexpected
CRCvalueforthe1Xor4Xmode.TheexpectedvalueiscomparedagainsttheCRCvalueattheendof
thereceivedpacket.
Afterthepacketreachesthelogicallayer,thepacketfieldsaredecodedandthepayloadisbuffered.
Dependingonthetypeofreceivedpacket,thepacketroutingishandledbyfunctionalblockswhichcontrol
theDMAaccess.
TheSRIOdatastreamconsistsofdatafieldspertainingtothelogicallayer,thetransportlayer,andthe
physicallayer.
•Thelogicallayerconsistsoftheheader(definingthetypeofaccess)andthepayload(ifpresent).
•Thetransportlayerispartiallydependentonthephysicaltopologyinthesystem,andconsistsof
sourceanddestinationIDsforthesendingandreceivingdevices.
•Thephysicallayerisdependentonthephysicalinterface(i.e.,serialversusparallelRapidIO)and
includespriority,acknowledgment,anderrorcheckingfields.
SRIOtransactionsarebasedonrequestandresponsepackets.Packetsarethecommunicationelement
betweenendpointdevicesinthesystem.Amasterorinitiatorgeneratesarequestpacketwhichis
transmittedtoatarget.Thetargetthengeneratesaresponsepacketbacktotheinitiatortocompletethe
transaction.
22SerialRapidIO(SRIO)SPRUE13A–September2006
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