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5.44QueuenReceiveDMACompletionPointerRegister(QUEUEn_RXDMA_CP)
SRIORegisters
Therearesixteenoftheseregisters(seeTable110).QUEUEn_RXDMA_CPisshowninFigure106and
describedinTable111.Foradditionalprogramminginformation,seeSection2.3.4.1.
Table110.QUEUEn_RXDMA_CPRegisters
RegisterAddressOffset
QUEUE0_RXDMA_CP0680h
QUEUE1_RXDMA_CP0684h
QUEUE2_RXDMA_CP0688h
QUEUE3_RXDMA_CP068Ch
QUEUE4_RXDMA_CP0690h
QUEUE5_RXDMA_CP0694h
QUEUE6_RXDMA_CP0698h
QUEUE7_RXDMA_CP069Ch
QUEUE8_RXDMA_CP06A0h
QUEUE9_RXDMA_CP06A4h
QUEUE10_RXDMA_CP06A8h
QUEUE11_RXDMA_CP06ACh
QUEUE12_RXDMA_CP06B0h
QUEUE13_RXDMA_CP06B4h
QUEUE14_RXDMA_CP06B8h
QUEUE15_RXDMA_CP06BCh
Figure106.QueuenReceiveDMACompletionPointerRegister(QUEUEn_RXDMA_CP)
310
RX_CP
R/W-00000000h
LEGEND:R/W=Read/Write;-n=Valueafterreset
Table111.QueuenReceiveDMACompletionPointerRegister(QUEUEn_RXDMA_CP)Field
Descriptions
BitFieldValueDescription
31–0RX_CP00000000hThisfieldisthememoryaddressforthereceivequeuecompletionpointer.This
toregisteriswrittenbytheDSPcorewiththebufferdescriptoraddressforthelast
FFFFFFFFhbufferprocessedbytheDSPcoreduringinterruptprocessing.Theportusesthe
valuewrittentodetermineiftheinterruptshouldbedeasserted.
SPRUE13A–September2006SerialRapidIO(SRIO)167
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