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5.40LSUnCongestionControlFlowMaskRegister(LSUn_FLOW_MASKS)
SRIORegisters
Therearefouroftheseregisters,oneforeachLSU(seeTable101).Thefieldsofan
LSUn_FLOW_MASKSregisteraresummarizedbyFigure101anddescribedinTable102.The16bits
withineachFLOW_MASKfieldaresummarizedbyFigure102andTable103.Foradditionalprogramming
seeSection2.3.8.
Table101.LSUn_FLOW_MASKSRegistersandtheAssociatedLSUs
RegisterAddressOffsetLSU
LSU1_FLOW_MASKS041ChLSU1
LSU2_FLOW_MASKS043ChLSU2
LSU3_FLOW_MASKS045ChLSU3
LSU4_FLOW_MASKS047ChLSU4
Figure101.LSUnCongestionControlFlowMaskRegister(LSUn_FLOW_MASKS)
3116150
ReservedFLOW_MASK
R-00hR/W-FFh
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table102.LSUnCongestionControlFlowMaskRegister(LSUn_FLOW_MASKS)FieldDescriptions
BitFieldValueDescription
31–16Reserved00hTheseread-onlybitsreturn0swhenread.
15–0FLOW_MASK00h-FFhFlowmaskforLSUn
Figure102.LSUnFLOW_MASKFields
1514131211109876543210
FL15FL14FL13FL12FL11FL10FL9FL8FL7FL6FL5FL4FL3FL2FL1FL0
R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1
LEGEND:R=Read;W=Write;-n=Valueafterreset
Table103.LSUnFLOW_MASKFields
BitFieldValueDescription
15FL150LSUndoesnotsupportFlow15fromtableentry
1LSUnsupportsFlow15fromtableentry
14FL140LSUndoesnotsupportFlow14fromtableentry
1LSUnsupportsFlow14fromtableentry
13FL130LSUndoesnotsupportFlow13fromtableentry
1LSUnsupportsFlow13fromtableentry
12FL120LSUndoesnotsupportFlow12fromtableentry
1LSUnsupportsFlow12fromtableentry
11FL110LSUndoesnotsupportFlow11fromtableentry
1LSUnsupportsFlow11fromtableentry
10FL100LSUndoesnotsupportFlow10fromtableentry
1LSUnsupportsFlow10fromtableentry
9FL90LSUndoesnotsupportFlow9fromtableentry
1LSUnsupportsFlow9fromtableentry
162SerialRapidIO(SRIO)SPRUE13A–September2006
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