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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-51
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Figure 4-35 MPU Region Size and Enable Registers format
Table 4-32 shows how the bit values correspond with the MPU Region Size and Enable
Registers.
To access an MPU Region Size and Enable Register, read or write CP15 with:
MRC p15, 0, <Rd>, c6, c1, 2 ; Read Data MPU Region Size and Enable Register
MCR p15, 0, <Rd>, c6, c1, 2 ; Write Data MPU Region Size and Enable Register
Writing a region size that is outside the range results in Unpredictable behavior.
c6, MPU Region Access Control Registers
The MPU Region Access Control Registers hold the region attributes and access permissions
for the region specified by the Memory Region Number Register.
Reserved Sub-region disable
31 65 0
Region size
1781516
Reserved
Enable
Table 4-32 Region Size Register bit functions
Bits Field Function
[31:16] Reserved SBZ.
[15:8] Sub-region disable
Each bit position represents a sub-region, 0-7
a
.
Bit [8] corresponds to sub-region 0
...
Bit [15] corresponds to sub-region 7
The meaning of each bit is:
0 = address range is part of this region
1 = address range is not part of this region.
Reserved SBZ.
[5:1] Region size Defines the region size:
b00000 - b00011=Unpredictable
b00100 = 32 bytes
b00101 = 64 bytes
b00110 = 128 bytes
b00111 = 256 bytes
b01000 = 512 bytes
b01001 = 1KB
b01010 = 2KB
b01011 = 4KB
b01100 = 8KB
b01101 = 16KB
b01110 = 32KB
b01111 = 64KB
b10000 = 128KB
b10001 = 256KB
b10010 = 512KB
b10011 = 1MB
b10100 = 2MB
b10101 = 4MB
b10110 = 8MB
b10111 = 16MB
b11000 = 32MB
b11001 = 64MB
b11010 = 128MB
b11011 = 256MB
b11100 = 512MB
b11101 = 1GB
b11110 = 2GB
b11111 = 4GB.
[0] Enable Enables or disables a memory region:
0 = Memory region disabled. Memory regions are disabled on reset.
1 = Memory region enabled. A memory region must be enabled before it is used.
a. Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant
addresses in the region. For more information, see Subregions on page 7-3.