Filter
Top Products
Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-8
ID013010 Non-Confidential, Unrestricted Access
The PMNC Register is always accessible in Privileged mode. To access the register, read or
write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 0 ; Read PMNC Register
MCR p15, 0, <Rd>, c9, c12, 0 ; Write PMNC Register
6.3.2 c9, Count Enable Set Register
The CouNT ENable Set (CNTENS) Register enables any of the performance monitor count
registers. When read, this register indicates which counters are enabled. Writing a 1 to a
particular count enable bit enables that counter. Writing a 0 to a count enable bit has no effect.
You must use the Count Enable Clear Register to disable the counters.
The CNTENS Register is:
• A read/write register.
• Always accessible in Privileged mode. The USEREN Register determines accessibility in
User mode, see c9, User Enable Register on page 6-15.
The values in this register are ignored unless the E bit, bit [0], is set in the PMNC Register, see
c9, Performance Monitor Control Register on page 6-7.
Figure 6-2 on page 6-9 shows the bit arrangement for the CNTENS Register.
[4] X Enable export of the events to the event bus for an external monitoring block, for example the
ETM, to trace events:
0 = Export disabled. This is the reset value.
1 = Export enabled.
[3] D Cycle count divider:
0 = Counts every processor clock cycle. This is the reset value.
1 = Counts every 64th processor clock cycle.
[2] C Cycle counter reset:
0 = no action
1 = reset cycle counter, CCNT, to zero.
This bit Reads-As-Zero.
[1] P Event counter reset:
0 = no action
1 = reset all event counters to zero.
This bit Reads-As-Zero.
[0] E Enable:
0 = Disable all counters, including CCNT. This is the reset value.
1 = Enable all counters including CCNT.
Table 6-2 PMNC Register bit functions (continued)
Bits Field Function