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Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-15
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6.3.9 c9, Performance Monitor Count Registers
There are three PMC Registers (PMC0-PMC2) in the processor. Each PMC Register, as selected
by the PMNXSEL Register, counts instances of an event selected by the EVTSEL Register. Bits
[31:0] of each PMC Register contain an event count. The register to be accessed is determined
by the value in the Performance Counter Selection Register.
Each PMC Register is:
• A read/write register
• Always accessible in Privileged mode. The USEREN Register determines access, see c9,
User Enable Register.
To access the current Performance Monitor Count Registers, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c13, 2 ; Read current PMNx Register
MCR p15, 0, <Rd>, c9, c13, 2 ; Write current PMNx Register
6.3.10 c9, User Enable Register
The USER ENable (USEREN) Register enables User mode to have access to:
• the performance monitor registers, see Performance monitoring registers on page 6-7
• the validation registers, see Validation Registers on page 4-62.
Note
The USEREN Register does not provide access to the registers that control interrupt generation.
The USEREN Register is:
• a read/write register
• writable only in Privileged mode, readable in any processor mode.
Figure 6-8 shows the bit arrangement for the USEREN Register.
Figure 6-8 USEREN Register format
Table 6-9 shows how the bit values correspond with the Performance Monitor Count Enable Set
Register.
If the EN bit in the USEREN Register is not set, any attempt to access a performance monitor
register or a validation register from User mode causes an Undefined instruction exception.
31 10
Reserved
EN
Table 6-9 USEREN Register bit functions
Bits Field Function
[31:1] Reserved RAZ or SBZP.
[0] EN User mode access to performance monitor and validation registers:
0 = Disabled. This is the reset value.
1 = Enabled.