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Level Two Interface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-19
ID013010 Non-Confidential, Unrestricted Access
The transactions shown in Table 9-24 on page 9-18 show this behavior. They are provided as
examples only, and are not an exhaustive description of the AXI transactions. Depending on the
state of the processor, and the timing of the accesses, the actual bursts generated might have a
different size and length to the examples shown, even for the same instruction.
If the same memory is marked as write-back Cacheable, and the addresses are allocated into a
cache line, no AXI write transactions occur until the cache line is evicted and performs a
write-back transaction. See Cache line write-back (eviction) on page 9-13.