Filter
Top Products
Processor Initialization, Resets, and Clocking
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-2
ID013010 Non-Confidential, Unrestricted Access
3.1 Initialization
Most of the architectural registers in the processor, such as r0-r14, and s0-s31 and d0-d15 when
floating-point is included, are not reset. Because of this, you must initialize these for all modes
before they are used, using an immediate-MOV instruction, or a PC-relative load instruction.
The Current Program Status Register (CPSR) is given a known value on reset. This is described
in the ARM Architecture Reference Manual. The reset values for the CP15 registers are
described along with the registers in Chapter 4 System Control Coprocessor.
In addition, before you run the application, you might want to:
• program particular values into various registers, for example, stack pointers
• enable various processor features, for example, error correction
• program particular values into memory, for example, the TCMs.
Other initialization requirements are described in:
• MPU
• CRS
• FPU
• Caches on page 3-3
• TCM on page 3-3.
3.1.1 MPU
If the processor has been built with an MPU, before you can use it you must:
• program and enable at least one of the regions
• enable the MPU in the System Control Register.
See c6, MPU memory region programming registers on page 4-49. Do not enable the MPU
unless at least one MPU region is programmed and active. If the MPU is enabled, before using
the TCM interfaces you must program MPU regions to cover the TCM regions to give access
permissions to them.
3.1.2 CRS
In processor revisions r1p2 and earlier the Call-Return-Stack (CRS) in the PFU is not reset. This
means it contains UNPREDICTABLE data after reset. ARM recommends that you initialize the
CRS before it is used. For more information on the PFU, see Chapter 5 Prefetch Unit,
To do this, before any return instructions are executed, such as
BX
,
LDR pc
, or
LDM pc
, execute
four branch-and-link instructions, as follows:
; Initialise call-return-stack (CRS) with four call instructions.
BL call1
call1 BL call2
call2 BL call3
call3 BL next
next
3.1.3 FPU
If the processor has been built with a Floating Point Unit (FPU) you must enable it before VFP
instructions can be executed:
• enable access to the FPU in the coprocessor access control register, see c1, Coprocessor
Access Register on page 4-44