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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-3
ID013010 Non-Confidential, Unrestricted Access
Figure 8-1 L1 memory system block diagram
AXI master
Instruction cache
controller and
RAMs
Data cache
controller and
RAMs
B0TCM
AXI bus
AXI bus
External Tightly-Coupled Memory (TCM)
AXI slave
Data Processing Unit (DPU)
Memory
Protection Unit
(MPU)
Prefetch Unit
(PFU)
Load Store Unit
(LSU)
Interconnect
ATCM B1TCM
Processor