ARM R4 Computer Hardware User Manual


 
Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-24
ID013010 Non-Confidential, Unrestricted Access
1.11 Product revision information
This manual is for major revision 1 of the processor. At the time of release, this includes the
r1p0, r1p1, r1p2, and r1p3 releases, although the vast majority of the information in this
document will also be applicable to any future r1px releases. The following broadly describes
the changes made in each subsequent revision of the processor:
Revision 1 Introduction of the ECC functional options and addition of the FPU options, to
implement the Cortex-R4F processor.
Note
The r1p0 release was not generally available.
1.11.1 Processor identification
The Cortex-R4 processor contains a number of IDentification (ID) registers that enable software
or a debugger to identify the processor as Cortex-R4, and the variant (major revision) and
revision (minor revision) of the design. These registers are:
Main ID Register (MIDR)
This register is accessible by software and identifies the part, the variant, and the
revision. See c0, Main ID Register on page 4-14. A copy of this register can also
be read by a debugger through the debug APB interface. See Processor ID
Registers on page 11-32.
Debug ID Register (DIDR)
This register can be read by a debugger through the debug APB interface, and by
software. It identifies the variant and revision. See CP14 c0, Debug ID Register
on page 11-10.
Peripheral ID Registers
These registers can be accessed through the debug APB interface only, and
identify the revision number of the processor. See Debug Identification Registers
on page 11-35.
Floating Point System ID Register (FPSID)
When the build-configuration includes the floating point unit, this register
identifies the revision number of the floating-point unit. See Floating-Point
System ID Register, FPSID on page 12-5.
Note
Floating point functionality is provided only with the Cortex-R4F processor.
The revision number of the processor, in the Peripheral ID and FPSID registers, is a single field
that incorporates information about both major and minor revisions.