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Cycles Per instruction (CPI)
Cycles per instruction (or clocks per instruction) is a measure of the number of computer
instructions that can be performed in one clock cycle. This figure of merit can be used to
compare the performance of different CPUs that implement the same instruction set against each
other. The lower the value, the better the performance.
CoreSight The infrastructure for monitoring, tracing, and debugging a complete system on chip.
Data Abort An indication from a memory system to the processor of an attempt to access an illegal data
memory location. An exception must be taken if the processor attempts to use the data that
caused the abort.
See also Abort, External Abort, and Prefetch Abort.
Data cache A block of on-chip fast access memory locations, situated between the processor and main
memory, used for storing and retrieving copies of often used data. This is done to greatly
increase the average speed of memory accesses and so improve processor performance.
Debugger A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
Default NaN mode A mode in which all operations that result in a NaN return the default NaN, regardless of the
cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all
information contained in any input NaNs to an operation is lost.
Denormalized value See Subnormal value.
Dirty A cache line in a write-back cache that has been modified while it is in the cache is said to be
dirty. A cache line is marked as dirty by setting the dirty bit. If a cache line is dirty, it must be
written to memory on a cache miss because the next level of memory contains data that has not
been updated. The process of writing dirty data to main memory is called cache cleaning.
See also Clean.
Disabled exception An exception is disabled when its exception enable bit in the FPCSR is not set. For these
exceptions, the IEEE 754 standard defines the result to be returned. An operation that generates
an exception condition can bounce to the support code to produce the result defined by the IEEE
754 standard. The exception is not reported to the user trap handler.
DNM See Do Not Modify.
Do Not Modify (DNM)
In Do Not Modify fields, the value must not be altered by software. DNM fields read as
Unpredictable values, and must only be written with the same value read from the same field on
the same processor. DNM fields are sometimes followed by RAZ or RAO in parentheses to
show which way the bits should read for future compatibility, but programmers must not rely on
this behavior.
Double-precision value
Consists of two 32-bit words that must appear consecutively in memory and must both be
word-aligned, and that is interpreted as a basic double-precision floating-point number
according to the IEEE 754-1985 standard.
Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
Embedded Trace Macrocell (ETM)
A hardware macrocell that, when connected to a processor core, outputs instruction and data
trace information on a trace port. The ETM provides processor driven trace through a trace port
compliant to the ATB protocol.
EmbeddedICE-RT The JTAG-based hardware provided by debuggable ARM processors to aid debugging in
real-time.