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Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-16
ID013010 Non-Confidential, Unrestricted Access
Note
For more information on access permissions to the performance monitor registers and validation
registers, see the ARM Architecture Reference Manual.
To access the USEREN Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 0 ; Read USEREN Register
MCR p15, 0, <Rd>, c9, c14, 0 ; Write USEREN Register
6.3.11 c9, Interrupt Enable Set Register
The INTerrupt ENable Set (INTENS) Register determines if any of the PMC Registers,
PMC0-PMC2 and CCNT, generate an interrupt request on overflow.
The INTENS Register is:
• a read/write register
• accessible in Privileged mode only.
Reading this register returns the current setting. Writing to this register can enable interrupts.
You can disable interrupts only by writing to the INTENC Register.
Figure 6-9 shows the bit arrangement for the INTENS Register.
Figure 6-9 INTENS Register format
Table 6-10 shows how the bit values correspond with the INTENS Register.
When reading bits [31], [2], [1], and [0] of the INTENS Register:
• 0 = interrupt disabled
• 1 = interrupt enabled.
When writing to bits [31], [2], [1], and [0] of the INTENS Register:
• 0 = no action
• 1 = interrupt enabled.
To access the Interrupt Enable Set Register, read or write CP15 with:
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter
overflow interrupt enables
Cycle count overflow interrupt enable
Table 6-10 INTENS Register bit functions
Bits Field Function
[31] C CCNT overflow interrupt enable
[30:3] Reserved UNP on reads, SBZP on write
[2] P2 PMC2 overflow interrupt enable
[1] P1 PMC1 overflow interrupt enable
[0] P0 PMC0 overflow interrupt enable