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Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-3
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[8] Exception return architecturally executed.
This event occurs on every exception return, for example,
RFE
,
MOVS
PC
,
LDM
PC^
.
-
0x0A
[9] Change to Context ID executed. -
0x0B
[10] Software change of PC, except by an exception, architecturally executed. -
0x0C
[11]
B
immediate,
BL
immediate or
BLX
immediate instruction architecturally
executed (taken or not taken).
-
0x0D
[12] Procedure return architecturally executed, other than exception returns, for
example,
BX Rm; LDM PC
.
MOV PC, LR
does not generate this event, because it is not predicted as a return.
-
0x0E
[13] Unaligned access architecturally executed.
This event occurs for each instruction that was to an unaligned address that
either triggered an alignment fault, or would have done so if the System
Control Register A-bit had been set.
-
0x0F
[14] Branch mispredicted or not predicted.
This event occurs for every pipeline flush caused by a branch.
-
0x10
N/A Cycle count. -
0x11
[15] Branches or other change in program flow that could have been predicted by
the branch prediction resources of the processor.
-
0x12
[16] Stall because instruction buffer cannot deliver an instruction.
This can indicate an ICache miss. This event occurs every cycle where the
condition is present.
-
0x40
[17] Stall because of a data dependency between instructions.
This event occurs every cycle where the condition is present.
-
0x41
[18] Data cache write-back.
This event occurs once for each line that is written back from the cache.
-
0x42
[19] External memory request.
Examples of this are cache refill, Non-cacheable accesses, write-through
writes, cache line evictions (write-back).
-
0x43
[20] Stall because of LSU being busy.
This event takes place each clock cycle where the condition is met. A high
incidence of this event indicates the pipeline is often waiting for transactions
to complete on the external bus.
-
0x44
[21] Store buffer was forced to drain completely.
Examples of this are
DMB
, Strongly Ordered memory access, or similar events.
-
0x45
N/A The number of cycles FIQ interrupts are disabled. -
0x46
N/A The number of cycles IRQ interrupts are disabled. -
0x47
N/A ETMEXTOUT[0]. -
0x48
N/A ETMEXTOUT[1]. -
0x49
Table 6-1 Event bus interface bit functions (continued)
EVNTBUS
bit position
Description
CFLR
update
Event
Ref.
Value