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Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-14
ID013010 Non-Confidential, Unrestricted Access
Figure 6-7 EVTSELx Register format
Table 6-8 shows how the bit values correspond with the EVTSELx Register.
To access the EVTSELx Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c13, 1 ; Read EVTSELx Register
MCR p15, 0, <Rd>, c9, c13, 1 ; Write EVTSELx Register
The absolute counts of events recorded might vary because of pipeline effects. This has
negligible effect except in cases where the counters are enabled for a very short time.
In addition to the counters within the processor, most of the events that Table 6-1 on page 6-2
shows are available to the ETM unit or other external trace hardware to enable monitoring of
the events. For information on how to monitor these events, see the CoreSight ETM-R4
Technical Reference Manual.
SEL
31 0
Reserved
87
Table 6-8 EVTSELx Register bit functions
Bits Field Function
[31:8] Reserved RAZ or SBZP.
[7:0] SEL Event number selected, see Table 6-1 on page 6-2 for
values.
The reset value of this field is Unpredictable.