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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-8
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External faults
A memory access performed through the AXI master interface can generate two different types
of error response, a slave error (SLVERR) or decode error (DECERR). These are known as
external errors, because they are generated by the AXI system outside the processor. Precise
aborts are generated for instruction fetches, data loads, and data stores to strongly-ordered-type
memory. Stores to normal-type or device-type memory generate imprecise aborts.
Note
An AXI slave that cannot handle exclusive transactions returns OKAY in response to an
exclusive read. This is also treated as an external error, and the processor behaves as if the
response was SLVERR.
Cache and TCM parity and ECC errors
If the processor has been configured with the appropriate build options, it can detect data errors
occurring in the cache and TCM RAMs using parity or ECC logic. For more information on
cache errors, see Handling cache parity errors on page 8-21 and Handling cache ECC errors
on page 8-22. For more information on TCM errors, see Handling TCM parity errors on
page 8-15 and Handling TCM ECC errors on page 8-15. Depending on the software
configuration of the processor, these errors are either ignored, generate an abort, are
automatically corrected without generating an abort, or are corrected and generate an abort. If
the processor is in debug-halt-state, an error that is otherwise automatically corrected generates
an abort.
Parity and ECC errors can only occur on reads, although these reads might be a side-effect of
store instructions. Aborts generated by loads are always precise. Aborts generated by store
instructions to the TCM are also always precise, while those to the cache are always imprecise.
These errors can also occur on some cache-maintenance operations, see Errors on cache
maintenance operations on page 8-23, and generate imprecise aborts.
Many of the parity and ECC errors are also signaled by the generation of events. See Chapter 6
Events and Performance Monitor. Some of these events are generated when the error is
detected, regardless of whether or not an abort is taken. Aborts are only taken when a memory
access with an error is committed. Others are signaled when and only when the abort is taken.
Any parity or ECC error that can be corrected by the processor is considered to be a correctable
fault, regardless of whether or not the processor is configured to correct the fault.
TCM external faults
The TCM port includes signals that can be used to signal an error on a TCM transaction. See the
Cortex-R4 and Cortex-R4F Integration Manual for more information about the TCM port. If
enabled, this causes the processor to take the appropriate type of abort for instruction and data
accesses, or to generate a SLVERR response to an AXI-slave transaction. Write transactions
always generate imprecise aborts, while read transactions always generate precise aborts.
An error signaled on a read transaction can also signal a retry request, which requests that the
processor retry the same operation rather than take an exception.
A retry request from the TCM port is considered to be a recoverable error. All correctable ECC
faults are also considered to be recoverable.