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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-44
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11.8 Debug state
The debug state enables an external agent, usually a debugger, to control the processor following
a debug event. While in debug state, the processor behaves as follows:
• The DSCR[0] core halted bit is set.
•The DBGACK signal is asserted, see DBGACK on page 11-51.
• The DSCR[5:2] method of entry bits are set appropriately.
• The processor is halted. The pipeline is flushed and no instructions are fetched.
• The processor does not change the execution mode. The CPSR is not altered.
• Exceptions are treated as described in Exceptions in debug state on page 11-47.
• Interrupts are ignored.
• New debug events are ignored.
The following sections describe:
• Entering debug state
• Behavior of the PC and CPSR in debug state on page 11-45
• Executing instructions in debug state on page 11-46
• Writing to the CPSR in debug state on page 11-46
• Privilege on page 11-46
• Accessing registers and memory on page 11-46
• Coprocessor instructions on page 11-47
• Effect of debug state on non-invasive debug on page 11-47
• Effects of debug events on processor registers on page 11-47
• Exceptions in debug state on page 11-47
• Leaving debug state on page 11-48.
11.8.1 Entering debug state
When a debug event occurs while the processor is in Halting debug-mode, it switches to a
special state called debug state so the debugger can take control. You can configure Halting
debug-mode by setting DSCR[14].
If a halting debug event occurs, the processor enters debug state even when Halting debug-mode
is not configured. While the processor is in debug state, the PC does not increment on instruction
execution. If the PC is read at any point after the processor has entered debug state, but before
an explicit PC write, it returns a value as described in Table 11-41, depending on the previous
state and the type of debug event.
Table 11-41 shows the read PC value after debug state entry for different debug events.
Table 11-41 Read PC value after debug state entry
Debug event ARM Thumb
Return address (RA
a
) meaning
Breakpoint RA+8 RA+4 Breakpointed instruction address.
Watchpoint RA+8 RA+4 Address of the instruction where the execution resumes. This
is several instructions after the one that hit the watchpoint.
BKPT
instruction RA+8 RA+4
BKPT
instruction address.