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Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-9
ID013010 Non-Confidential, Unrestricted Access
The EmbeddedICE-RT logic supports two modes of debug operation:
Halt mode On a debug event, such as a breakpoint or watchpoint, the debug logic stops the
processor and forces it into debug state. This enables you to examine the internal
state of the processor, and the external state of the system, independently from
other system activity. When the debugging process completes, the processor and
system state are restored, and normal program execution resumes.
Monitor debug mode
On a debug event, the processor generates a debug exception instead of entering
debug state, as in halt mode. The exception entry enables a debug monitor
program to debug the processor while enabling critical interrupt service routines
to operate on the processor. The debug monitor program can communicate with
the debug host over the DCC or any other communications interface in the
system.
1.3.7 System control coprocessor
The system control coprocessor provides configuration and control of the memory system and
its associated functionality. Other system-level operations, such as memory barrier instructions,
are also managed through the system control coprocessor.
For more information, see System control and configuration on page 4-4.
1.3.8 Interrupt handling
Interrupt handling in the processor is compatible with previous ARM architectures, but has
several additional features to improve interrupt performance for real-time applications.
VIC port
The core has a dedicated port that enables an external interrupt controller, such as the ARM
PrimeCell Vectored Interrupt Controller (VIC), to supply a vector address along with an
Interrupt Request (IRQ) signal. This provides faster interrupt entry, but you can disable it for
compatibility with earlier interrupt controllers.
Note
If you do not have a VIC in your design, you must ensure the nIRQ and nFIQ signals are
asserted, held LOW, and remain LOW until the exception handler clears them.
Low interrupt latency
On receipt of an interrupt, the processor abandons any pending restartable memory operations.
Restartable memory operations are the multiword transfer instructions
LDM
,
LDRD
,
STRD
,
STM
,
PUSH
,
and
POP
that can access Normal memory.
To minimize the interrupt latency, ARM recommends that you do not perform:
• multiple accesses to areas of memory marked as Device or Strongly Ordered
• SWP operations to slow areas of memory.
Exception processing
The ARMv7-R architecture contains exception processing instructions to reduce interrupt
handler entry and exit time:
SRS Save return state to a specified stack frame.