ARM R4 Computer Hardware User Manual


 
Introduction
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Instruction and data caches
You can configure the processor to include separate instruction and data caches. The caches
have the following features:
Support for independent configuration of the instruction and data cache sizes between
4KB and 64KB.
Pseudo-random cache replacement policy.
8-word cache line length. Cache lines can be either write-back or write-through,
determined by MPU region.
Ability to disable each cache independently.
Streaming of sequential data from
LDM
and
LDRD
operations, and sequential instruction
fetches.
Critical word first filling of the cache on a cache miss.
Implementation of all the cache RAM blocks and the associated tag and valid RAM
blocks using standard ASIC RAM compilers
Parity or ECC supported on local memories.
Memory Protection Unit
An optional MPU provides memory attributes for embedded control applications. You can
configure the MPU to have eight or twelve regions, each with a minimum resolution of 32 bytes.
MPU regions can overlap, and the highest numbered region has the highest priority.
The MPU checks for protection and memory attributes, and some of these can be passed to an
external L2 memory system.
For more information, see Chapter 7 Memory Protection Unit.
TCM interfaces
Because some applications might not respond well to caching, there are two TCM interfaces that
permit connection to configurable memory blocks of Tightly-Coupled Memory (ATCM and
BTCM). These ensure high-speed access to code or data. As an option, the BTCM can have two
memory ports for increased bandwidth.
An ATCM typically holds interrupt or exception code that must be accessed at high speed,
without any potential delay resulting from a cache miss.
A BTCM typically holds a block of data for intensive processing, such as audio or video
processing.
You can individually configure the TCM blocks at any naturally aligned address in the memory
map. Permissible TCM block sizes are:
•0KB
•4KB
•8KB
16KB
32KB
64KB
128KB
256KB