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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-12
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c7 0 c11 1 Clean data cache line by
physical address to
Point-of-Unification
Write-only - page 4-55
2-7 Undefined - - -
c12-c13 0-7
c14 0
1 Clean and invalidate data
cache line by physical
address to
Point-of-Unification
Write-only - page 4-55
c14 2 Clean and invalidate data
cache line by Set/Way
Write-only - page 4-55
3-7 Undefined - - -
c15 0-7
c8 0 c0-c15 0-7 Undefined - - -
c9 0 c0 0-7 Undefined - - -
c1 0 BTCM Region Read/write
-
d
page 4-57
1 ATCM Region Read/write
-
d
page 4-57
2-7 Undefined - - -
c2 0 TCM selection Read/write
0x00000000
page 4-59
1-7 Undefined - - -
c3-c11 0-7
c12 0 Performance Monitor
Control
Read/write
0x41141800
page 6-7
1 Count Enable Set Read/write Unpredictable page 6-8
2 Count Enable Clear Read/write Unpredictable page 6-9
3 Overflow Flag Status Read/write Unpredictable page 6-10
4 Software Increment Write-only - page 6-11
c9 0 c12 5 Performance Counter
Selection
Read/write Unpredictable page 6-12
6-7 Undefined - - -
c13 0 Cycle Count Read/write
0x00000000
page 6-13
1 Event Select Read/write Unpredictable page 6-13
2 Performance Monitor
Count
Read/write
0x00000000
page 6-15
3-7 Undefined - - -
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page