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Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-20
ID013010 Non-Confidential, Unrestricted Access
1.9 Test features
The processor is delivered as fully-synthesizable RTL and is a fully-static design. Scan-chains
and test wrappers for production test can be inserted into the design by the synthesis tools during
implementation. See the relevant reference methodology documentation for more information.
Production test of the processor cache and TCM RAMs can be done through the dedicated,
pipelined MBIST interface. This interface shares some of the multiplexing present in the
processor design, which improves the potential frequency compared to adding multiplexors to
the RAM modules. See the Cortex-R4 and Cortex-R4F Integration Manual for more
information about this interface, and how to control it.
In addition, you can use the AXI slave interface to read and write the cache and TCM RAMs.
You can use this feature to test the cache RAMs in a running system. This might be required in
a safety-critical system. The TCM RAMs can be read and written directly by the program
running on the processor. You can also use the AXI slave interface for swapping a test program
in to the TCMs for the processor to execute. See Accessing RAMs using the AXI slave interface
on page 9-24 for more information about how to access the RAMs using the AXI slave interface.