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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-30
ID013010 Non-Confidential, Unrestricted Access
14.20 Floating-point load/store instructions
This section describes the cycle timing behavior for all load and store instructions that operate
on the VFP register file:
• The base address register, and any offset register are Very Early Regs for both loads and
stores.
• For store instructions, the data register (Sd or Dd), or registers are always Late Regs.
• The cycle timing of load and store instructions is affected by the starting address for the
transfer.
Note
The starting address is not always the same as the base address.
• The cycle timing of load and store multiple instructions is also affected by whether or not
the base address register is updated by the instruction, that is, base register writeback.
Table 14-25 shows the number of cycles and result latencies for single load and store
instructions and load multiple instructions. Values are shown for each instruction with and
without base register writeback, and with different starting address alignments. Cycle counts
and base register result latencies for store multiple instructions are the same as for the equivalent
load multiple instruction.
Table 14-25 Floating-point load/store instructions cycle timing behavior
Example instruction
Cycles/
memory
cycles
Cycles with
writeback (!)
Result
latency
(load)
Result
latency
(base
register,
<Rn>)
Comments
VLDR.32 <Sd>, [<Rn>{, #+/-<imm>}]
1- 1- -
VLDR.64 <Dd>, [<Rn>{, #+/-<imm>}]
1 - 1 - 64-bit aligned address
VLDR.64 <Dd>, [<Rn>{, #+/-<imm>}]
2 - 2 - Not aligned
VSTR.32 <Sd>, [<Rn>{, #+/-<imm>}]
1- -- -
VSTR.64 <Dd>, [<Rn>{, #+/-<imm>}]
1 - - - 64-bit aligned address
VSTR.64 <Dd>, [<Rn>{, #+/-<imm>}]
2 - - - Not aligned
First address 64-bit aligned
VLDM{mode}.32 <Rn>{!}, {s1}
11 11 -
VLDM{mode}.32 <Rn>{!}, {s1,s2}
1 2 1,1 2 -
VLDM{mode}.32 <Rn>{!}, {s1-s3}
2 2 1,1,2 2 -
VLDM{mode}.32 <Rn>{!}, {s1-s4}
2 3 1,1,2,2 3 -
VLDM{mode}.64 <Rn>{!}, {d1}
12 12 -
VLDM{mode}.64 <Rn>{!}, {d1,d2}
2 3 1,2 3 -
VLDM{mode}.64 <Rn>{!}, {d1-d3}
3 4 1,2,3 4 -
VLDM{mode}.64 <Rn>{!}, {d1-d4}
4 5 1,2,3,4 5 -