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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
107
User’s Manual U10676EJ3V0UM
Figure 6-15. Format of Processor Clock Control Register
PCC3
3210
FB3H
Address
PCC
Symbol
PCC2 PCC1 PCC0
CPU operating mode control bits
PCC3 PCC2 Operating mode
0 0 Normal operating mode
0 1 HALT mode
1 0 STOP mode
1 1 Setting prohibited
CPU clock selection bits
(
µ
PD754144: When fCC = 1.0 MHz)
PCC1 PCC0 CPU clock frequency 1 machine cycle
00Φ = f
CC/64 (15.6 kHz) 64
µ
s
01Φ = fCC/16 (62.5 kHz) 16
µ
s
10Φ = fCC/8 (125 kHz) 8
µ
s
11Φ = fCC/4 (250 kHz) 4
µ
s
(
µ
PD754244: When fX = 6.0 MHz)
PCC1 PCC0 CPU clock frequency 1 machine cycle
00Φ = fX/64 (93.8 kHz) 10.7
µ
s
01Φ = fX/16 (375 kHz) 2.67
µ
s
10Φ = fX/8 (750 kHz) 1.33
µ
s
11Φ = fX/4 (1.5 MHz) 0.67
µ
s
(
µ
PD754244: When fX = 4.19 MHz)
PCC1 PCC0 CPU clock frequency 1 machine cycle
00Φ = fX/64 (65.5 kHz) 15.3
µ
s
01Φ = fX/16 (262 kHz) 3.81
µ
s
10Φ = fX/8 (524 kHz) 1.91
µ
s
11Φ = fX/4 (1.05 MHz) 0.95
µ
s
Remark fCC and fX: System clock oscillation frequency