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CHAPTER 6 PERIPHERAL HARDWARE FUNCTION
152 User’s Manual U10676EJ3V0UM
Figure 6-40. Setting of Timer Counter Mode Registers
TM20TM21TM23 TM22TM24TM25TM26–
TM2
F90H
TM23
Clears counter and IRQTn flag when "1" is written. Starts count operation
if bit 2 is set to "1".
Timer start command bit
Operation mode
TM22
0
1
Stops (count value retained)
Count operation
Count operation
Count pulse (CP) select bit
TMn6
TM1
TMn5
0
Overflow of count register (T2)
1
f
X2
5
10
01
1
f
X/2
10
0
fX/2
8
fX/2
12
TMn4
0
1
0
1
110
fX/2
6
111
Operation mode select bit
TM21
1 16-bit timer counter mode
ModeTM20
0
765432
10
TM10TM11TM13 TM12TM14TM15TM16–
Address
TM1
FA8H
Symbol
TM2
fX/2
fX
fX/2
8
fX/2
6
fX/2
10
fX/2
4
TM11
1
TM10
0
Setting prohibited
Other
Remark n = 1 and 2