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Appendix D Register Map and Descriptions
© National Instruments Corporation D-7 Lab-PC+ User Manual
Status Register
The Status Register indicates the status of the current A/D conversion. The bits in this register
determine if a conversion is being performed or if data is available, whether any errors have been
found, and the interrupt status.
Address: Base address + 00 (hex)
Type: Read-only
Word Size: 8-bit
Bit Map:
76543210
Lab-PC/PC+ EXTGATA0 GATA0 DMATC CNTINT OVERFLOW OVERRUN DAVAIL
Bit Name Description
7 Lab-PC/PC+ This bit indicates whether the board is a Lab-PC or a Lab-PC+. If
this bit is 0, a Lab-PC+ is present. If this bit is 1, a Lab-PC is
present.
6 EXTGATA0 This bit indicates the status of the external trigger. If this bit is set,
the external trigger signal has been received to trigger a data
acquisition operation. This bit is cleared by writing to ADCLR
Register.
5 GATA0 This bit indicates the status of the GATE 0 input on the
counter/timer chip (Counter Group A). This bit can be used as a
busy indicator for data acquisition operations because conversions
are enabled as long as GATE 0 is high and Counter A0 is
programmed appropriately.
4 DMATC This bit reflects the status of the DMA terminal count. If this bit is
set, and if the TCINTEN bit is set in Command Register 3, then the
current interrupt is due to the detection of a DMA terminal counter
pulse. This bit is cleared by writing to the DMATC Interrupt Clear
Register.
3 CNTINT This bit reflects the status of the interrupt caused by Counter A2
output or the EXTUPDATE signal. If the CNTINTEN bit in
Command Register 3 is set, a low-to-high transition on Counter A2
output or on EXTUPDATE sets this bit and generates an interrupt
request. This bit is cleared by writing to the CNTINTCLR
Register.
2 OVERFLOW This bit indicates if an overflow error has occurred. If this bit is
cleared, no error was encountered. If this bit is set, the A/D FIFO
has overflowed because the data acquisition servicing operation
could not keep up with the sampling rate.