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Register Map and Descriptions Appendix D
Lab-PC+ User Manual D-10 © National Instruments Corporation
Bit Name Description (continued)
2 SWTRIG This bit enables and disables a data acquisition operation that is
controlled by Counter A0 and Counter A1. If Counter A0 is
programmed for data acquisition, writing 1 to this bit enables
Counter A0, and thus starts a data acquisition operation. A data
acquisition process is terminated either by the terminal count signal
of Counter A1 or by clearing SWTRIG. If SWTRIG is cleared, the
Counter A0 is disabled, except when the HWTRIG mode is used.
1 HWTRIG Setting this bit allows the external EXTTRIG signal to start a data
acquisition operation that is controlled by Counter A0 and
Counter A1. If this bit is set, a low-to-high transition on
EXTTRIG enables Counter A0, and thus starts a data acquisition
operation. To use this mode, the SWTRIG and PRETRIG bits
should be cleared.
0 PRETRIG This bit is used to set the pretriggering feature on the Lab-PC+. If
this bit is set, a data acquisition operation is initialized by setting
SWTRIG, but the Counter A1 (the sample counter) does not begin
decrementing until a rising edge is detected on EXTTRIG. To use
this mode, the HWTRIG bit should be cleared.