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Appendix E Register-Level Programming
© National Instruments Corporation E-13 Lab-PC+ User Manual
3. Program Counter A0.
Since a high-to-low transition on the Counter A0 output initiates an A/D conversion,
Counter A0 output must be programmed to a high state. This ensures that Counter A0 does
not cause any A/D conversions.
Write 34 (hex) to the Counter A Mode Register (select Counter A0, Mode 2) to force OUT0
to a high state. This is an 8-bit operation.
4. Clear the A/D circuitry.
Before the data acquisition operation is started, the A/D FIFO must be emptied in order to
clear any old A/D conversion results. This emptying must be performed after the counters
are programmed in case any spurious edges were caused while programming the counters.
Write 0 to the A/D Clear Register to empty the FIFO (8-bit write) and read from the A/D
FIFO (8-bit read) twice. Ignore the obtained data.
5. Program Counter A1.
Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter
counts the number of A/D conversions and disable conversions when the programmed count
is reached. The sample count must be less than or equal to 65,535. The minimum sample
count is three.
To program the counters, use the following programming sequence:
a. Write 70 (hex) to the Counter A Mode Register (select Counter A1, Mode 0). This step
sets the output of Counter A1 (OUTA1) low.
b. Write the least significant byte of (M-2), where M is the sample count, to the Counter A1
Data Register.
c. Write the most significant byte of (M-2), where M is the sample count, to the Counter A1
Data Register.
6. Select posttrigger mode and enable EXTCONV* and EXTTRIG input.
Set the HWTRIG bit in Command Register 2. This setting enables EXTTRIG and
EXTCONV*; that is, the first rising edge on EXTTRIG starts the data acquisition sequence.
7. Service the data acquisition operation.
Once the data acquisition operation is started by a rising edge on the EXTTRIG input, A/D
conversions are initiated by falling edges on the EXTCONV* input. The operation must be
serviced by reading the A/D FIFO Register every time an A/D conversion result becomes
available. To service the data acquisition, perform the following sequence until the desired
number of conversion results have been read:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.
DMA or interrupts can also be used to service the data acquisition operation. These topics are
discussed in the A/D Interrupt Programming and Programming DMA Operation sections later in
this appendix.