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Register-Level Programming Appendix E
Lab-PC+ User Manual E-14 © National Instruments Corporation
Two error conditions may occur during a data acquisition operation: an overflow error or an
overrun error. These error conditions are reported through the Status Register and should be
checked every time the Status Register is read to check the DAVAIL bit.
An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D
FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more
data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is cleared.
An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is low. The minimum
recommended sampling interval on the Lab-PC+ is 16 µs.
Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D
Clear Register.
Pretrigger Mode
The following programming steps are required for a data acquisition operation in controlled
acquisition mode using EXTCONV*. In the following programming sequence, EXTTRIG is
used as a pretrigger signal; that is, A/D conversions are enabled but the sample count is not
started until a rising edge is detected on the EXTTRIG input. Data acquisition remains enabled
for the programmed count after the rising edge on the EXTTRIG input. Thus, data can be
acquired before and after the trigger (EXTTRIG).
1. Select analog input channel and gain and select pretrigger mode.
The analog input channel and gain are selected by writing to Command Register 1. The
SCANEN bit must be cleared for data acquisition operations on a single channel. See the bit
description for Command Register 1 earlier in this chapter for gain and analog input channel
bit descriptions. To select pretrigger mode, set the PRETRIG bit and clear the HWTRIG bit
in Command Register 2.