Filter
Top Products
Appendix E Register-Level Programming
© National Instruments Corporation E-17 Lab-PC+ User Manual
Pretrigger Mode
Pretriggering mode requires that the A/D conversions be shut off at a programmed time by the
hardware after the trigger on EXTTRIG. Therefore, pretriggered data acquisition is not possible
in freerun acquisition mode.
Programming Multiple A/D Conversions with
Channel Scanning
The data acquisition programming sequences given earlier in this chapter are for programming
the Lab-PC+ for multiple A/D conversions on a single input channel. The Lab-PC+ can also be
programmed for scanning analog input channels during the data acquisition operation. Analog
channels N through 0 can be scanned, where N can be 1 through 7. Programming scanned
multiple A/D conversions involves the same sequence of steps as single-channel data acquisition
operations except that the SCANEN bit is set in Command Register 1. When the SCANEN bit is
set in Command Register 1, the analog channel select bits MA<2..0> specify the highest
numbered channel in the scan sequence. For example, if MA<2..0> is 011 (binary)–that is,
Channel 3 is selected and the SCANEN bit is set–the following scan sequence is used:
Channel 3, Channel 2, Channel 1, Channel 0, Channel 3, Channel 2, Channel 1, Channel 0,
Channel 3, and so on.
Note: Selecting the analog input channel and gain should be performed in the following
order:
1. Write the configuration value indicating the highest channel number in the scan
sequence, the gain, and the input polarity to Command Register 1. The SCANEN
bit must be cleared during this first write to Command Register 1.
2. Write the same configuration value again to Command Register 1. The SCANEN
bit, however, must be set during the second write to Command Register 1.
Scanning can be enabled in either controlled or freerun acquisition mode. Either Counter A0 or
EXTCONV* can be used to control the scanning interval.
Programming Multiple A/D Conversions with
Interval Scanning
In addition to scanning multiple channels, the Lab-PC+ can also use interval scanning if more
than one channel is being scanned. If the INTSCAN bit in the Configuration Register is set,
interval scanning is enabled and a single channel-scanning cycle is performed for every pulse
received on the OUTB1 line on the I/O connector. This signal may be driven by Counter B1 or
by an external source. A channel-scanning cycle consists of the sequence of back-to-back
conversions performed while channels N through 0 are sampled; the duration of a channel-
scanning cycle is N+1 times the sample interval (determined by Counter A0 or EXTCONV*).
An interval-scanning cycle consists of a channel-scanning cycle followed by a time period in
which no conversions are performed. The duration of an interval-scanning cycle is equal to the
period of the signal present on the OUTB1 line. The period of this signal must be at least as long
as the channel-scanning cycle. While using the interval-scanning mode, the SCANEN bit in the
Analog Configuration Register is used to gate the operation of the INTSCAN bit until the data