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Appendix E Register-Level Programming
© National Instruments Corporation E-15 Lab-PC+ User Manual
2. Program Counter A0.
Since a high-to-low transition on the Counter A0 output initiates an A/D conversion,
Counter A0 output must be programmed to a high state. This ensures that Counter A0 does
not cause any A/D conversions.
Write 34 (hex) to the Counter A Mode Register (select Counter A0, Mode 2) to force OUTO
to a high state. This is an 8-bit operation.
3. Clear the A/D circuitry.
Before the data acquisition operation is started, the A/D FIFO must be emptied in order to
clear any old A/D conversion results. This emptying must be performed after the counters
are programmed in case any spurious edges were caused while programming the counters.
Write 0 to the A/D Clear Register to empty the FIFO (8-bit write) and to read from the A/D
FIFO (8-bit read) twice. Ignore the data obtained. In pretrigger mode, a write to the A/D
Clear Register also sets the GATA1 bit low. A/D conversions are not counted until GATA1
is set high by a rising edge on the EXTTRIG input.
4. Program Counter A1 and enable EXTCONV* input.
Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter
counts the number of A/D conversions and disable conversions when the programmed count
is reached. The sample count must be less than or equal to 65,535. The minimum sample
count is 2.
To program the counters, use the following programming sequence.
a. Write 70 (hex) to the Counter A Mode Register (select Counter A1, Mode 0). This step
sets the output of Counter A1 (OUTA1) low, which in turn, enables EXTCONV*; that is,
falling edges on EXTCONV* initiate A/D conversions.
b. Write the least significant byte of (M), where M is the sample count, after the trigger to
the Counter A1 Data Register.
c. Write the most significant byte of (M), where M is the sample count, after the trigger to
the Counter A1 Data Register.
After you complete this programming sequence, counter A1 is configured to count A/D
conversion pulses and EXTTRIG input is enabled.