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Lab-PC+ User Manual viii © National Instruments Corporation
Figures
Figure 1-1. The Relationship between the Programming Environment,
NI-DAQ, and Your Hardware............................................................................ 1-3
Figure 2-1. Parts Locator Diagram ....................................................................................... 2-2
Figure 2-2. Example Base I/O Address Switch Settings ...................................................... 2-4
Figure 2-3. DMA Jumper Settings for DMA Channel 3 (Factory Setting) .......................... 2-6
Figure 2-4. DMA Jumper Settings for Disabling DMA Transfers ....................................... 2-7
Figure 2-5. Interrupt Jumper Setting IRQ5 (Factory Setting) .............................................. 2-7
Figure 2-6. Interrupt Jumper Setting for Disabling Interrupts.............................................. 2-8
Figure 2-7. Bipolar Output Jumper Configuration (Factory Setting) ................................... 2-9
Figure 2-8. Unipolar Output Jumper Configuration ............................................................. 2-10
Figure 2-9. DIFF Input Configuration .................................................................................. 2-12
Figure 2-10. RSE Input Configuration ................................................................................... 2-12
Figure 2-11. NRSE Input Configuration................................................................................. 2-13
Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting)...................................... 2-14
Figure 2-13. Unipolar Input Jumper Configuration................................................................ 2-14
Figure 3-1. Lab-PC+ I/O Connector Pin Assignments......................................................... 3-2
Figure 3-2. Lab-PC+ Instrumentation Amplifier.................................................................. 3-5
Figure 3-3. Differential Input Connections for Grounded Signal Sources ........................... 3-8
Figure 3-4. Differential Input Connections for Floating Sources ......................................... 3-9
Figure 3-5. Single-Ended Input Connections for Floating Signal Sources........................... 3-11
Figure 3-6. Single-Ended Input Connections for Grounded Signal Sources ........................ 3-12
Figure 3-7. Analog Output Signal Connections.................................................................... 3-13
Figure 3-8. Digital I/O Connections ..................................................................................... 3-15
Figure 3-9. EXTCONV* Signal Timing............................................................................... 3-21
Figure 3-10. Posttrigger Data Acquisition Timing Case 1 ..................................................... 3-22
Figure 3-11. Posttrigger Data Acquisition Timing Case 2 ..................................................... 3-22
Figure 3-12. Pretrigger Data Acquisition Timing................................................................... 3-23
Figure 3-13. EXTUPDATE* Signal Timing for Updating DAC Output ............................... 3-24
Figure 3-14. EXTUPDATE* Signal Timing for Generating Interrupts ................................. 3-24
Figure 3-15. Event-Counting Application with External Switch Gating................................ 3-25
Figure 3-16. Frequency Measurement Application ................................................................ 3-26
Figure 3-17. General-Purpose Timing Signals ....................................................................... 3-27
Figure 4-1. Lab-PC+ Block Diagram ................................................................................... 4-1
Figure 4-2. PC I/O Interface Circuitry Block Diagram ........................................................ 4-3
Figure 4-3. Analog Input and Data Acquisition Circuitry Block Diagram .......................... 4-4
Figure 4-4. Analog Output Circuitry Block Diagram........................................................... 4-9
Figure 4-5. Digital I/O Circuitry Block Diagram ................................................................. 4-10
Figure 4-6. Timing I/O Circuitry Block Diagram................................................................. 4-12
Figure 4-7. Two-Channel Interval-Scanning Timing ........................................................... 4-13
Figure 4-8. Single-Channel Interval Timing......................................................................... 4-14
Figure 4-9. Counter Block Diagram ..................................................................................... 4-14
Figure 5-1. Calibration Trimpot Location Diagram ............................................................. 5-2
Figure E-1. Control-Word Format with Control-Word Flag Set to 1 ................................... E-24
Figure E-2. Control-Word Format with Control-Word Flag Set to 0 ................................... E-24